Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/6826
Change subject: alpha,arm,mips,power,riscv,sparc,x86: Get rid of
TheISA::NoopMachInst.
......................................................................
alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.
It's no longer used.
Change-Id: I4a71bcb214f1bb186b92ef50841eca635e6701c5
---
M src/arch/alpha/isa_traits.hh
M src/arch/arm/isa_traits.hh
M src/arch/mips/isa_traits.hh
M src/arch/power/isa_traits.hh
M src/arch/riscv/isa_traits.hh
M src/arch/sparc/isa_traits.hh
M src/arch/x86/isa_traits.hh
7 files changed, 0 insertions(+), 35 deletions(-)
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index a383fe4..61688b5 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -108,10 +108,6 @@
const int MachineBytes = 8;
-// return a no-op instruction... used for instruction fetch faults
-// Alpha UNOP (ldq_u r31,0(r0))
-const ExtMachInst NoopMachInst = 0x2ffe0000;
-
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 185c764..5763e77 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -93,9 +93,6 @@
// Max. physical address range in bits supported by the architecture
const unsigned MaxPhysAddrRange = 48;
- // return a no-op instruction... used for instruction fetch faults
- const ExtMachInst NoopMachInst = 0x01E320F000ULL;
-
const int MachineBytes = 4;
const uint32_t HighVecs = 0xFFFF0000;
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index c0b1b9d..6e08c7e 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -139,9 +139,6 @@
mode_number // number of modes
};
-// return a no-op instruction... used for instruction fetch faults
-const ExtMachInst NoopMachInst = 0x00000000;
-
const int ANNOTE_NONE = 0;
const uint32_t ITOUCH_ANNOTE = 0xffffffff;
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index fa13483..9afe680 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -60,9 +60,6 @@
const int MachineBytes = 4;
-// This is ori 0, 0, 0
-const ExtMachInst NoopMachInst = 0x60000000;
-
// Memory accesses can be unaligned
const bool HasUnalignedMemAcc = true;
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 93f984b..abafad2 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -60,8 +60,6 @@
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
-const ExtMachInst NoopMachInst = 0x00000013;
-
// Memory accesses can be unaligned (at least for double-word memory
accesses)
const bool HasUnalignedMemAcc = true;
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 0db5a12..58d8437 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -44,9 +44,6 @@
// This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
-// SPARC NOP (sethi %(hi(0), g0)
-const MachInst NoopMachInst = 0x01000000;
-
// real address virtual mapping
// sort of like alpha super page, but less frequently used
const Addr SegKPMEnd = ULL(0xfffffffc00000000);
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 00c5e9b..158e2f9 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -53,10 +53,6 @@
//are used.
using namespace LittleEndianGuest;
- // X86 NOP (XCHG rAX, rAX)
- //XXX This needs to be set to an intermediate instruction struct
- //which encodes this instruction
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
@@ -65,19 +61,6 @@
const bool CurThreadInfoImplemented = false;
const int CurThreadInfoReg = -1;
-
- const ExtMachInst NoopMachInst M5_VAR_USED = {
- 0x0, // No legacy prefixes.
- 0x0, // No rex prefix.
- 0x0, // No two / three byte escape
sequence
- { OneByteOpcode, 0x90 }, // One opcode byte, 0x90.
- 0x0, 0x0, // No modrm or sib.
- 0, 0, // No immediate or displacement.
- 8, 8, 8, // All sizes are 8.
- 0, // Displacement size is 0.
- SixtyFourBitMode // Behave as if we're in 64 bit
- // mode (this doesn't actually
matter).
- };
}
#endif // __ARCH_X86_ISATRAITS_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4a71bcb214f1bb186b92ef50841eca635e6701c5
Gerrit-Change-Number: 6826
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
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