B.A. Zeeb has uploaded this change for review. (
https://gem5-review.googlesource.com/6841
Change subject: configs: add option for l3cache, cache_config
......................................................................
configs: add option for l3cache, cache_config
Start introducing a way to configure (enable/disable) an L3 cache.
While going through this also allow L2 size/assoc to not be specified.
Add an option to specify a specific cache configuration. This highly
simplifies testing multiple models/configurations independent of the
CPU model and without having to specify gazillions of command line
options.
Change-Id: I1cdb7cfa929f6cf1b0f916506efece64df5bd341
---
M configs/common/CacheConfig.py
M configs/common/Caches.py
M configs/common/Options.py
M src/mem/XBar.py
4 files changed, 89 insertions(+), 17 deletions(-)
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index a0a18a3..c9fd5e8 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -46,7 +46,8 @@
from Caches import *
def config_cache(options, system):
- if options.external_memory_system and (options.caches or
options.l2cache):
+ if options.external_memory_system and (options.caches or
options.l2cache
+ or options.l3cache):
print "External caches and internal caches are exclusive
options.\n"
sys.exit(1)
@@ -60,47 +61,85 @@
print "O3_ARM_v7a_3 is unavailable. Did you compile the O3
model?"
sys.exit(1)
- dcache_class, icache_class, l2_cache_class, walk_cache_class = \
- O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \
- O3_ARM_v7aWalkCache
+ dcache_class, icache_class = O3_ARM_v7a_DCache, O3_ARM_v7a_ICache
+ l2_cache_class, l3_cache_class = O3_ARM_v7aL2, None
+ walk_cache_class = O3_ARM_v7aWalkCache
else:
- dcache_class, icache_class, l2_cache_class, walk_cache_class = \
- L1_DCache, L1_ICache, L2Cache, None
+ dcache_class, icache_class, l2_cache_class, l3_cache_class = \
+ L1_DCache, L1_ICache, L2Cache, L3Cache
+ walk_cache_class = None
if buildEnv['TARGET_ISA'] == 'x86':
walk_cache_class = PageTableWalkerCache
+ if options.cache_config is not None:
+ try:
+ from importlib import import_module
+ #from options.cache_config import *
+ ccmod = import_module(options.cache_config)
+ except:
+ print "%s cache config failed to load" % (options.cache_config)
+ raise
+
+ dcache_class, icache_class, l2_cache_class, l3_cache_class = \
+ getattr(ccmod, options.cache_config + "_DCache"), \
+ getattr(ccmod, options.cache_config + "_ICache"), \
+ getattr(ccmod, options.cache_config + "_L2"), \
+ getattr(ccmod, options.cache_config + "_L3")
+
# Set the cache line size of the system
- system.cache_line_size = options.cacheline_size
+ if options.cacheline_size is not None:
+ system.cache_line_size = options.cacheline_size
# If elastic trace generation is enabled, make sure the memory system
is
# minimal so that compute delays do not include memory access
latencies.
# Configure the compulsory L1 caches for the O3CPU, do not configure
# any more caches.
- if options.l2cache and options.elastic_trace_en:
- fatal("When elastic trace is enabled, do not configure L2 caches.")
+ if (options.l3cache or options.l2cache) and options.elastic_trace_en:
+ fatal("When elastic trace is enabled, do not configure L2/3
caches.")
+
+ if options.l3cache and l3_cache_class is not None:
+ system.l3cache = l3_cache_class(clk_domain=system.cpu_clk_domain)
+ system.tol3bus = L3XBar(clk_domain = system.cpu_clk_domain)
+ if options.l3_size is not None:
+ system.l3cache.size=options.l3_size
+ if options.l3_assoc is not None:
+ system.l3cache.assoc=options.l3_assoc
+ system.l3cache.cpu_side = system.tol3bus.master
+ system.l3cache.mem_side = system.membus.slave
if options.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs.
- system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
- size=options.l2_size,
- assoc=options.l2_assoc)
+ system.l2cache = l2_cache_class(clk_domain=system.cpu_clk_domain)
+ if options.l2_size is not None:
+ system.l2cache.size=options.l2_size
+ if options.l2_assoc is not None:
+ system.l2cache.assoc=options.l2_assoc
system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.l2.cpu_side = system.tol2bus.master
- system.l2.mem_side = system.membus.slave
+ if options.l3cache and l3_cache_class is not None:
+ system.l2.mem_side = system.tol3bus.slave
+ else:
+ system.l2.mem_side = system.membus.slave
if options.memchecker:
system.memchecker = MemChecker()
for i in xrange(options.num_cpus):
if options.caches:
- icache = icache_class(size=options.l1i_size,
- assoc=options.l1i_assoc)
- dcache = dcache_class(size=options.l1d_size,
- assoc=options.l1d_assoc)
+ icache = icache_class()
+ if options.l1i_size is not None:
+ icache.size=options.l1i_size
+ if options.l1i_assoc is not None:
+ icache.assoc=options.l1i_assoc
+ dcache = dcache_class()
+ if options.l1d_size is not None:
+ dcache.size=options.l1d_size
+ if options.l1d_assoc is not None:
+ dcache.assoc=options.l1d_assoc
# If we have a walker cache specified, instantiate two
# instances here
@@ -155,6 +194,9 @@
ExternalCache("cpu%d.dcache" % i))
system.cpu[i].createInterruptController()
+ if options.l3cache and l3_cache_class is not None:
+ system.cpu[i].connectCachedPorts(system.tol2bus)
+ system.cpu[i].connectUncachedPorts(system.membus)
if options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
elif options.external_memory_system:
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 926a41d..931742e 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -72,6 +72,15 @@
tgts_per_mshr = 12
write_buffers = 8
+class L3Cache(Cache):
+ assoc = 20
+ tag_latency = 50
+ data_latency = 50
+ response_latency = 50
+ mshrs = 512
+ tgts_per_mshr = 20
+ write_buffers = 256
+
class IOCache(Cache):
assoc = 8
tag_latency = 50
diff --git a/configs/common/Options.py b/configs/common/Options.py
index ea7c75b..ef6990d 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -98,6 +98,7 @@
help="use external port for SystemC TLM
cosimulation")
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")
+ parser.add_option("--l3cache", action="store_true")
parser.add_option("--num-dirs", type="int", default=1)
parser.add_option("--num-l2caches", type="int", default=1)
parser.add_option("--num-l3caches", type="int", default=1)
@@ -110,6 +111,8 @@
parser.add_option("--l2_assoc", type="int", default=8)
parser.add_option("--l3_assoc", type="int", default=16)
parser.add_option("--cacheline_size", type="int", default=64)
+ parser.add_option("--cache_config", type="string",
+ help="Select a sepcifc cache configuration")
# Enable Ruby
parser.add_option("--ruby", action="store_true")
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index 655d980..117caf7 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -148,6 +148,24 @@
# to the first level of unified cache.
point_of_unification = True
+# We use a coherent crossbar to connect multiple masters to the L3
+# cache.
+class L3XBar(CoherentXBar):
+ # 256-bit crossbar by default
+ width = 32
+
+ # Assume that most of this is covered by the cache latencies, with
+ # no more than a single pipeline stage for any packet.
+ frontend_latency = 1
+ forward_latency = 0
+ response_latency = 1
+ snoop_response_latency = 1
+
+ # Use a snoop-filter by default, and set the latency to zero as
+ # the lookup is assumed to overlap with the frontend latency of
+ # the crossbar
+ snoop_filter = SnoopFilter(lookup_latency = 0)
+
# One of the key coherent crossbar instances is the system
# interconnect, tying together the CPU clusters, GPUs, and any I/O
# coherent masters, and DRAM controllers.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1cdb7cfa929f6cf1b0f916506efece64df5bd341
Gerrit-Change-Number: 6841
Gerrit-PatchSet: 1
Gerrit-Owner: B.A. Zeeb <[email protected]>
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