Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/6621 )
Change subject: arch-arm: Hyp routed undef fault need to change its syndrome
......................................................................
arch-arm: Hyp routed undef fault need to change its syndrome
If undefined instruction has to be routed to EL2, the HSR register
must change the HSR.EC and HSR.ISS accordingly, which means not using
the EL1 exception syndrome, but the unknown reason one (EC=0, ISS=0)
Change-Id: I1540c713ab545bf307c1dad3ae305de4178443f4
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Nikos Nikoleris <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/6621
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 27 insertions(+), 8 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 8d019d5..d143056 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -391,6 +391,7 @@
uint32_t value;
uint32_t exc_class = (uint32_t) ec(tc);
uint32_t issVal = iss();
+
assert(!from64 || ArmSystem::highestELIs64(tc));
value = exc_class << 26;
@@ -438,12 +439,15 @@
from64 = true;
// Determine target exception level
- if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc))
+ if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) {
toEL = EL3;
- else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc))
+ } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) {
toEL = EL2;
- else
+ hypRouted = true;
+ } else {
toEL = opModeToEL(nextMode());
+ }
+
if (fromEL > toEL)
toEL = fromEL;
@@ -486,12 +490,14 @@
armInst->annotateFault(this);
}
- if (have_security && routeToMonitor(tc))
+ if (have_security && routeToMonitor(tc)) {
cpsr.mode = MODE_MON;
- else if (have_virtualization && routeToHyp(tc))
+ } else if (have_virtualization && routeToHyp(tc)) {
cpsr.mode = MODE_HYP;
- else
+ hypRouted = true;
+ } else {
cpsr.mode = nextMode();
+ }
// Ensure Secure state if initially in Monitor mode
if (have_security && saved_cpsr.mode == MODE_MON) {
@@ -747,6 +753,12 @@
uint32_t
UndefinedInstruction::iss() const
{
+
+ // If UndefinedInstruction is routed to hypervisor, iss field is 0.
+ if (hypRouted) {
+ return 0;
+ }
+
if (overrideEc == EC_INVALID)
return issRaw;
@@ -836,7 +848,12 @@
ExceptionClass
UndefinedInstruction::ec(ThreadContext *tc) const
{
- return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
+ // If UndefinedInstruction is routed to hypervisor,
+ // HSR.EC field is 0.
+ if (hypRouted)
+ return EC_UNKNOWN;
+ else
+ return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
}
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 3191ceb..fa6740a 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -73,6 +73,8 @@
ExceptionLevel toEL; // Target exception level
OperatingMode fromMode; // Source operating mode
+ bool hypRouted; // True if the fault has been routed to Hypervisor
+
Addr getVector(ThreadContext *tc);
Addr getVector64(ThreadContext *tc);
@@ -173,7 +175,7 @@
ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
machInst(_machInst), issRaw(_iss), from64(false), to64(false),
- fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED) {}
+ fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED), hypRouted(false)
{}
// Returns the actual syndrome register to use based on the target
// exception level
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I1540c713ab545bf307c1dad3ae305de4178443f4
Gerrit-Change-Number: 6621
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
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