Hi Christian,
I'm getting started implementing FS mode for RISC-V, but I haven't gotten
very far yet. So far, I've determined that it comes down to two things in
general: support for RISC-V's privileged architecture, and a compatible
Linux kernel and disk image. Since you only need to run bare-metal
applications, it sounds like you are more interested in the implementation
of the privileged architecture. I'm not very familiar with running
bare-metal applications on gem5, but a disk image may also be necessary.
To support the privileged architecture, there are a few components that
need to be implemented:
- A proper CSR file, including side effects
- Privilege levels, including ECALL and {U|S|M}RET instructions
- Proper fault handling (right now faults all simply cause panics)
- Interrupts
There may be more, but I haven't looked beyond these yet. It will also be
important to make sure that the atomic memory instructions are actually
atomic with multithreading, which Tuan Ta at Cornell University is working
on. I'm working on the CSRs right now and plan to do privilege levels next.
As for custom instructions, the only way to do that would be to modify the
ISA description (in src/arch/riscv/). If you don't need to define new
types of instructions, you can focus on src/arch/riscv/isa/decoder.isa,
which defines the operation each instruction performs. Other behaviors are
defined by the instruction formats in src/arch/riscv/isa/formats/ and
definitions for each type of instruction are in src/arch/riscv/insts/. If
you have any specific questions about the current ISA definition or on how
to implement certain kinds of instructions, I'd be happy to help.
-Alec Roelke
On Thu, Jan 11, 2018 at 4:37 AM, Christian Menard <
[email protected]> wrote:
> Hi all,
>
> I have a student who is interested in extending the RISC-V support in
> gem5 as part of his Master's thesis. The focus would be to enable FS
> support (at least for bare-metal applications, not necessarily for
> Linux) and to define an interface for the addition of user defined
> custom instructions. The goal would be to simulate a full embedded
> system with a user defined custom instruction set.
>
> I know that some people here are working on RISC-V and I would like to
> sync up before we actually start our work. Is somebody already working
> in this direction? Are you aware of any problems that might be in the
> way? Do you have an idea on what would be a good way to implement custom
> instructions for RISC-V?
>
> Cheers,
>
> Christian
>
>
> --
> Dipl.-Ing. Christian Menard
> Research Assistant
>
> TU Dresden
> Faculty of Computer Science
> Chair for Compiler Construction
> 01062 Dresden
>
> Phone: +49 351 463-42441
> e-Mail: [email protected]
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