Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/7643
Change subject: riscv: Add overrides to various StaticInst methods.
......................................................................
riscv: Add overrides to various StaticInst methods.
This makes riscv compile with the version of clang(++) I have on my
workstation.
Change-Id: I0478616810fbc8a715fd61323b7e0f73676c8328
---
M src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/isa/formats/amo.isa
M src/arch/riscv/isa/formats/basic.isa
M src/arch/riscv/isa/formats/mem.isa
M src/arch/riscv/isa/formats/standard.isa
5 files changed, 24 insertions(+), 17 deletions(-)
diff --git a/src/arch/riscv/insts/static_inst.hh
b/src/arch/riscv/insts/static_inst.hh
index bf34c9b..073b60c 100644
--- a/src/arch/riscv/insts/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -75,23 +75,27 @@
~RiscvMacroInst() { microops.clear(); }
- StaticInstPtr fetchMicroop(MicroPC upc) const { return microops[upc]; }
+ StaticInstPtr
+ fetchMicroop(MicroPC upc) const override
+ {
+ return microops[upc];
+ }
Fault
- initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
+ initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
override
{
panic("Tried to execute a macroop directly!\n");
}
Fault
completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ Trace::InstRecord *traceData) const override
{
panic("Tried to execute a macroop directly!\n");
}
Fault
- execute(ExecContext *xc, Trace::InstRecord *traceData) const
+ execute(ExecContext *xc, Trace::InstRecord *traceData) const override
{
panic("Tried to execute a macroop directly!\n");
}
diff --git a/src/arch/riscv/isa/formats/amo.isa
b/src/arch/riscv/isa/formats/amo.isa
index e3be237..1dca571 100644
--- a/src/arch/riscv/isa/formats/amo.isa
+++ b/src/arch/riscv/isa/formats/amo.isa
@@ -51,10 +51,11 @@
// Constructor
%(class_name)sLoad(ExtMachInst machInst, %(class_name)s *_p);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, Trace::InstRecord *) const
override;
+ Fault initiateAcc(ExecContext *,
+ Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const;
+ Trace::InstRecord *) const override;
};
class %(class_name)sStore : public %(base_class)sMicro
@@ -63,10 +64,11 @@
// Constructor
%(class_name)sStore(ExtMachInst machInst, %(class_name)s *_p);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, Trace::InstRecord *) const
override;
+ Fault initiateAcc(ExecContext *,
+ Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const;
+ Trace::InstRecord *) const override;
};
};
}};
diff --git a/src/arch/riscv/isa/formats/basic.isa
b/src/arch/riscv/isa/formats/basic.isa
index bb8401e..dd25ba6 100644
--- a/src/arch/riscv/isa/formats/basic.isa
+++ b/src/arch/riscv/isa/formats/basic.isa
@@ -40,7 +40,7 @@
public:
/// Constructor.
%(class_name)s(MachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, Trace::InstRecord *) const override;
using %(base_class)s::generateDisassembly;
};
}};
diff --git a/src/arch/riscv/isa/formats/mem.isa
b/src/arch/riscv/isa/formats/mem.isa
index d4c1754..a932d01 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -43,9 +43,10 @@
/// Constructor.
%(class_name)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
- Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *)
const;
+ Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
override;
+ Fault completeAcc(PacketPtr, ExecContext *,
+ Trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index ebe1571..2e0e3ed 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -43,7 +43,7 @@
public:
/// Constructor.
%(class_name)s(MachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const override;
};
@@ -99,7 +99,7 @@
public:
/// Constructor.
%(class_name)s(MachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const
override;
@@ -158,7 +158,7 @@
public:
/// Constructor.
%(class_name)s(MachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const
override;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0478616810fbc8a715fd61323b7e0f73676c8328
Gerrit-Change-Number: 7643
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
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