Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/8021 )

Change subject: arch-arm: Don't change PSTATE in Illegal Exception return
......................................................................

arch-arm: Don't change PSTATE in Illegal Exception return

This patch fixes the Illegal Exception return handler. According to the
armarm documentation, when PSTATE.IL is set to one because of an illegal
exception return, PSTATE.{EL, nRW, SP} are unchanged. This means the
Exception level, Execution state, and stack pointer selection do not
change as a result of the return.

Change-Id: I35f2fe68fb2822a54fc4a21930871eab7a1aaab4
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8021
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa.cc
2 files changed, 11 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index aace1de..a7ba91e 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1018,7 +1018,17 @@
     new_cpsr.ss = 0;

     if (illegalExceptionReturn(tc, cpsr, spsr)) {
+        // If the SPSR specifies an illegal exception return,
+        // then PSTATE.{M, nRW, EL, SP} are unchanged and PSTATE.IL
+        // is set to 1.
         new_cpsr.il = 1;
+        if (cpsr.width) {
+            new_cpsr.mode = cpsr.mode;
+        } else {
+            new_cpsr.width = cpsr.width;
+            new_cpsr.el = cpsr.el;
+            new_cpsr.sp = cpsr.sp;
+        }
     } else {
         new_cpsr.il = spsr.il;
         if (spsr.width && badMode32((OperatingMode)(uint8_t)spsr.mode)) {
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index c917aba..5d34e18 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -726,7 +726,7 @@
         CPSR old_cpsr = miscRegs[MISCREG_CPSR];
         int old_mode = old_cpsr.mode;
         CPSR cpsr = val;
-        if (old_mode != cpsr.mode) {
+        if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
             getITBPtr(tc)->invalidateMiscReg();
             getDTBPtr(tc)->invalidateMiscReg();
         }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I35f2fe68fb2822a54fc4a21930871eab7a1aaab4
Gerrit-Change-Number: 8021
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
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