Sujay Phadke has uploaded this change for review. (
https://gem5-review.googlesource.com/8401
Change subject: Merge branch 'master' of
https://gem5.googlesource.com/public/gem5
......................................................................
Merge branch 'master' of https://gem5.googlesource.com/public/gem5
Change-Id: I0ca6d11d4d44eb79f501e628fd4584352fcecef5
---
M ext/git-commit-msg
M src/arch/alpha/ev5.cc
3 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/ext/git-commit-msg b/ext/git-commit-msg
index 60fe59d..b07ec4a 100755
--- a/ext/git-commit-msg
+++ b/ext/git-commit-msg
@@ -1,5 +1,5 @@
#!/bin/sh
-# From Gerrit Code Review 2.13.5-2617-gba50ae91fd
+# From Gerrit Code Review 2.15-rc2-2157-g1438975847
#
# Part of Gerrit Code Review (https://www.gerritcodereview.com/)
#
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 2f3a9c3..ae8efa4 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -303,11 +303,7 @@
if (tc->getKernelStats())
tc->getKernelStats()->mode(Kernel::kernel, tc);
}
-<<<<<<< HEAD (f6d1b6 scons: fix for no 'break' in the case statement)
- break;
-=======
M5_FALLTHROUGH;
->>>>>>> BRANCH (80427e arch-arm: IMPLEMENTATION DEFINED register)
case IPR_ICM:
// only write two mode bits - processor mode
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0ca6d11d4d44eb79f501e628fd4584352fcecef5
Gerrit-Change-Number: 8401
Gerrit-PatchSet: 1
Gerrit-Owner: Sujay Phadke <[email protected]>
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