Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/8881
to review the following change.
Change subject: arch-arm: ERET from AArch64 to AArch32 ignore MSBs
......................................................................
arch-arm: ERET from AArch64 to AArch32 ignore MSBs
The 32 most significant bits of ELR_ELx must be ignored when returning
from AArch64 to AArch32.
Change-Id: I412d72908997916404e16e9eeca2789a9c529e58
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa/insts/branch64.isa
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/src/arch/arm/isa/insts/branch64.isa
b/src/arch/arm/isa/insts/branch64.isa
index 64457b8..8ef9f93 100644
--- a/src/arch/arm/isa/insts/branch64.isa
+++ b/src/arch/arm/isa/insts/branch64.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2011-2013, 2016 ARM Limited
+// Copyright (c) 2011-2013, 2016,2018 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -120,12 +120,19 @@
mnemonic);
break;
}
- if (spsr.width && (newPc & mask(2))) {
- // To avoid PC Alignment fault when returning to
AArch32
- if (spsr.t)
- newPc = newPc & ~mask(1);
- else
- newPc = newPc & ~mask(2);
+ if (spsr.width) {
+ // Exception return to AArch32.
+ // 32 most significant bits are ignored
+ newPc &= mask(32);
+
+ if (newPc & mask(2)) {
+ // Mask bits to avoid PC Alignment fault when
returning
+ // to AArch32
+ if (spsr.t)
+ newPc = newPc & ~mask(1);
+ else
+ newPc = newPc & ~mask(2);
+ }
}
CPSR new_cpsr = getPSTATEFromPSR(xc->tcBase(), cpsr, spsr);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I412d72908997916404e16e9eeca2789a9c529e58
Gerrit-Change-Number: 8881
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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