Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/8961
Change subject: arch-x86: Implement rdtscp instruction
......................................................................
arch-x86: Implement rdtscp instruction
This is essentially the same as rdtsc except it writes ecx, too.
This instruction should write the value of TSC_AUX to ecx, but this patch
simply puts 0 in ecx.
Change-Id: I03de94e1269dae4ebedd1bdba400c56f2c59acf9
Signed-off-by: Jason Lowe-Power <[email protected]>
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/insts/system/msrs.py
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index aa60e4c..761e838 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -133,7 +133,7 @@
0x7: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x0: Inst::SWAPGS();
- 0x1: rdtscp();
+ 0x1: Inst::RDTSCP();
default: Inst::UD2();
}
default: Inst::INVLPG(M);
diff --git a/src/arch/x86/isa/insts/system/msrs.py
b/src/arch/x86/isa/insts/system/msrs.py
index d0e2675..f540e8d 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -65,4 +65,13 @@
srli t1, t1, 32, dataSize=8
mov rdx, rdx, t1, dataSize=4
};
+
+def macroop RDTSCP
+{
+ rdtsc t1
+ mov rax, rax, t1, dataSize=4
+ srli t1, t1, 32, dataSize=8
+ mov rdx, rdx, t1, dataSize=4
+ xor rcx, rcx, rcx
+};
'''
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I03de94e1269dae4ebedd1bdba400c56f2c59acf9
Gerrit-Change-Number: 8961
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: newchange
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