Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/9044
Change subject: x86: Simplify the implementations of RDTSC and RDTSCP
slightly.
......................................................................
x86: Simplify the implementations of RDTSC and RDTSCP slightly.
These instructions originally read the TSC into t1 and then unpacked it
into eax and edx using a move, a right shift, and then another move.
We can combine the second shift and move. The shift will move the
upper 32 bits into the lower 32 bits, and clear the upper 32 bits to
zero. This has the same effect as moving the lower 32 bits post-shift
into another register, since the upper 32 bits will be cleared to zero
based on x86 partial register access semantics.
Change-Id: Iba85e501c7e84147ad0047f5c555e61bdf8f032b
---
M src/arch/x86/isa/insts/system/msrs.py
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/arch/x86/isa/insts/system/msrs.py
b/src/arch/x86/isa/insts/system/msrs.py
index b79b6db..04020ef 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -63,8 +63,7 @@
.serialize_before
rdtsc t1
mov rax, rax, t1, dataSize=4
- srli t1, t1, 32, dataSize=8
- mov rdx, rdx, t1, dataSize=4
+ srli rdx, t1, 32, dataSize=8
};
def macroop RDTSCP
@@ -73,8 +72,7 @@
mfence
rdtsc t1
mov rax, rax, t1, dataSize=4
- srli t1, t1, 32, dataSize=8
- mov rdx, rdx, t1, dataSize=4
+ srli rdx, t1, 32, dataSize=8
rdval rcx, "InstRegIndex(MISCREG_TSC_AUX)", dataSize=4
};
'''
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iba85e501c7e84147ad0047f5c555e61bdf8f032b
Gerrit-Change-Number: 9044
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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