Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/9161
Change subject: arch-riscv: Add support for fault handling
......................................................................
arch-riscv: Add support for fault handling
This patch adds support for handling RISC-V faults, including tracking
current and previous execution privilege, correctly switching to
the privilege mode specified by CSRs, and setting/storing the PC.
Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9
---
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/registers.hh
4 files changed, 67 insertions(+), 62 deletions(-)
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 4e44d43..ce50149 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -30,6 +30,7 @@
*/
#include "arch/riscv/faults.hh"
+#include "arch/riscv/registers.hh"
#include "arch/riscv/utility.hh"
#include "cpu/thread_context.hh"
#include "sim/debug.hh"
@@ -48,6 +49,26 @@
{
if (FullSystem) {
panic("Full system mode not supported for RISC-V.");
+ MiscRegIndex cause = MISCREG_MCAUSE;
+ MiscRegIndex epc = MISCREG_MEPC;
+ MISCREG prv = 0x3;
+ if (bits(tc->readMiscReg(MISCREG_PRV), 1) == 0
+ && bits(tc->readMiscReg(MISCREG_MEDELEG), _code) != 0) {
+ cause = MISCREG_SCAUSE;
+ epc = MISCREG_SEPC;
+ prv = 0x1;
+ }
+ if (tc->readMiscReg(MISCREG_PRV) == 0
+ && bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) {
+ cause = MISCREG_UCAUSE;
+ epc = MISCREG_UEPC;
+ prv = 0x0;
+ }
+ tc->writeMiscReg(cause,
+ (_interrupt << (sizeof(MiscReg) * 4 - 1)) |
_code);
+ tc->writeMiscReg(epc, tc->instAddr());
+ tc->writeMiscReg(MISCREG_PRV, prv);
+
} else {
invoke_se(tc, inst);
PCState pcState = tc->pcState();
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index 1e33b64..61f2781 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -34,17 +34,20 @@
#include <string>
+#include "arch/riscv/registers.hh"
#include "cpu/thread_context.hh"
#include "sim/faults.hh"
namespace RiscvISA
{
-const uint32_t FloatInexact = 1 << 0;
-const uint32_t FloatUnderflow = 1 << 1;
-const uint32_t FloatOverflow = 1 << 2;
-const uint32_t FloatDivZero = 1 << 3;
-const uint32_t FloatInvalid = 1 << 4;
+enum FloatException : MiscReg {
+ FloatInexact = 0x1,
+ FloatUnderflow = 0x2,
+ FloatOverflow = 0x4,
+ FloatDivZero = 0x8,
+ FloatInvalid = 0x10
+};
enum ExceptionCode {
INST_ADDR_MISALIGNED = 0,
@@ -59,71 +62,50 @@
AMO_ACCESS = 7,
ECALL_USER = 8,
ECALL_SUPER = 9,
- ECALL_HYPER = 10,
- ECALL_MACH = 11
-};
-
-enum InterruptCode {
- SOFTWARE,
- TIMER
+ ECALL_MACHINE = 11,
+ INST_PAGE = 12,
+ LOAD_PAGE = 13,
+ STORE_PAGE = 15,
+ AMO_PAGE = 15
};
class RiscvFault : public FaultBase
{
protected:
const FaultName _name;
+ bool _interrupt;
const ExceptionCode _code;
- const InterruptCode _int;
- RiscvFault(FaultName n, ExceptionCode c, InterruptCode i)
- : _name(n), _code(c), _int(i)
+ RiscvFault(FaultName n, bool i, ExceptionCode c)
+ : _name(n), _interrupt(i), _code(c)
{}
- FaultName
- name() const
- {
- return _name;
- }
+ FaultName name() const { return _name; }
+ bool isInterrupt() const { return _interrupt; }
+ ExceptionCode exception() const { return _code; }
- ExceptionCode
- exception() const
- {
- return _code;
- }
-
- InterruptCode
- interrupt() const
- {
- return _int;
- }
-
- virtual void
- invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
-
- void
- invoke(ThreadContext *tc, const StaticInstPtr &inst);
+ virtual void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+ void invoke(ThreadContext *tc, const StaticInstPtr &inst);
};
class UnknownInstFault : public RiscvFault
{
public:
- UnknownInstFault() : RiscvFault("Unknown instruction", INST_ILLEGAL,
- SOFTWARE)
+ UnknownInstFault() : RiscvFault("Unknown instruction", false,
INST_ILLEGAL)
{}
- void
- invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+ void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
};
class IllegalInstFault : public RiscvFault
{
private:
const std::string reason;
+
public:
IllegalInstFault(std::string r)
- : RiscvFault("Illegal instruction", INST_ILLEGAL, SOFTWARE),
- reason(r)
+ : RiscvFault("Illegal instruction", false, INST_ILLEGAL)
{}
void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
@@ -133,25 +115,26 @@
{
private:
const std::string instName;
+
public:
UnimplementedFault(std::string name)
- : RiscvFault("Unimplemented instruction", INST_ILLEGAL, SOFTWARE),
- instName(name)
+ : RiscvFault("Unimplemented instruction", false, INST_ILLEGAL),
+ instName(name)
{}
- void
- invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+ void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
};
class IllegalFrmFault: public RiscvFault
{
private:
const uint8_t frm;
+
public:
IllegalFrmFault(uint8_t r)
- : RiscvFault("Illegal floating-point rounding mode", INST_ILLEGAL,
- SOFTWARE),
- frm(r)
+ : RiscvFault("Illegal floating-point rounding mode", false,
+ INST_ILLEGAL),
+ frm(r)
{}
void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
@@ -160,11 +143,8 @@
class BreakpointFault : public RiscvFault
{
public:
- BreakpointFault() : RiscvFault("Breakpoint", BREAKPOINT, SOFTWARE)
- {}
-
- void
- invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+ BreakpointFault() : RiscvFault("Breakpoint", false, BREAKPOINT) {}
+ void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
};
class SyscallFault : public RiscvFault
@@ -172,11 +152,8 @@
public:
// TODO: replace ECALL_USER with the appropriate privilege level of the
// caller
- SyscallFault() : RiscvFault("System call", ECALL_USER, SOFTWARE)
- {}
-
- void
- invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
+ SyscallFault() : RiscvFault("System call", false, ECALL_USER) {}
+ void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
};
} // namespace RiscvISA
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 71d8cef..8aa64b3 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -80,6 +80,9 @@
sstatus.fs = 0x1;
sstatus.uxl = 0x2;
}
+
+ // 0x0 = user; 0x1 = supervisor; 0x3 = machine
+ miscRegFile[MISCREG_PRV] = 0x3;
}
bool
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 874f923..121c909 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -83,7 +83,7 @@
// This has to be one to prevent warnings that are treated as errors
const unsigned NumVecRegs = 1;
const int NumCCRegs = 0;
-const int NumMiscRegs = 4096;
+const int NumMiscRegs = 4097;
// Semantically meaningful register indices
const int ZeroReg = 0;
@@ -193,7 +193,11 @@
MISCREG_TDATA3 = 0x7A3,
MISCREG_DCSR = 0x7B0,
MISCREG_DPC = 0x7B1,
- MISCREG_DSCRATCH = 0x7B2
+ MISCREG_DSCRATCH = 0x7B2,
+
+ // This register should not be accessible by software; to accomplish
that,
+ // its index lies outside the range of possible 12-bit values
+ MISCREG_PRV = 0x1000
};
const std::map<int, std::string> MiscRegNames = {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9
Gerrit-Change-Number: 9161
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke <ar...@virginia.edu>
Gerrit-MessageType: newchange
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