Nikos,
It was only once, so I don't know what might be the cause. If I ever experience
it again, I will let you know.
Regards,Daniel
Em quinta-feira, 22 de março de 2018 15:46:16 GMT+1, Nikos Nikoleris
<[email protected]> escreveu:
Hi Daniel,
I am afraid, I can't reproduce the error you're experiencing, and the outputs
from your runs are not very telling of the problem. I run the
realview-simple-atomic-checkpoint regression at:
* 68af229490fc811aebddf68b3e2e09e63a5fa475 and
* 0473286ab1e9992a906eff380000bf90c82eeccb
and both of them passed.
Nikos
On 22/03/2018, 14:17, "gem5-dev on behalf of Daniel Carvalho"
<[email protected] on behalf of [email protected]> wrote:
While running the regression tests while at master commit
68af229490fc811aebddf68b3e2e09e63a5fa475, one of the tests failed with the
following output:
--- quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-checkpoint ---
*** gem5: ERROR: gem5 exited with non-zero status: 1
gem5 exited with non-zero status: 1
*** gem5 stderr ***
*** m5out/simerr ***
info: kernel located at:
PATH_TO_GEM5/FullSystemImages/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file:
PATH_TO_GEM5/FullSystemImages/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
at address 0x88000000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0. Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
warn: Returning zero for read from miscreg pmcr
warn: Ignoring write of 0x80000000 to miscreg pmcntenclr
warn: Ignoring write of 0x80000000 to miscreg pmintenclr
warn: Ignoring write of 0x80000000 to miscreg pmovsr
warn: Ignoring write of 0x6 to miscreg pmcr
Test failed.
*** gem5 stdout ***
*** m5out/simout ***
Redirecting stdout to
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-checkpoint/simout
Redirecting stderr to
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-checkpoint/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Mar 22 2018 13:51:32
gem5 started Mar 22 2018 13:53:18
gem5 executing on OMITTED_MACHINE_NAME, pid 12855
command line: PATH_TO_GEM5/gem5/build/ARM/gem5.opt -d
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-checkpoint
--stats-file 'text://stats.txt?desc=False' -re
PATH_TO_GEM5/gem5/tests/testing/../run.py
quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-checkpoint
Global frequency set at 1000000000000 ticks per second
Test failed: Unknown exit cause: user interrupt received
*****
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-checkpoint:
FAILED!
I've then updated head to the following commit
(0473286ab1e9992a906eff380000bf90c82eeccb), and the same test passed. As it
also passed using a commit that has still not been rebased to 0473
(https://gem5-review.googlesource.com/c/public/gem5/+/8501), they were likely
lucky runs.
Hope this is useful for the maintainer.
Att,Daniel
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