Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/9302
Change subject: mem-cache: Fix FALRU data block seg fault
......................................................................
mem-cache: Fix FALRU data block seg fault
FALRU didn't initialize the blocks' data, causing seg faults.
This patch does not make FALRU functional yet.
Change-Id: I10cbcf5afc3f8bc357eeb8b7cb46789dec47ba8b
---
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/fa_lru.cc
5 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 8b52b74..d2d6e8e 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -63,7 +63,8 @@
std::max(p->tag_latency, p->data_latency)),
cache(nullptr),
warmupBound((p->warmup_percentage/100.0) * (p->size /
p->block_size)),
- warmedUp(false), numBlocks(p->size / p->block_size)
+ warmedUp(false), numBlocks(p->size / p->block_size),
+ dataBlks(new uint8_t[p->size]) // Allocate data storage in one big
chunk
{
}
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 74fc7e0..3370de2 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -94,6 +94,9 @@
/** the number of blocks in the cache */
const unsigned numBlocks;
+ /** The data blocks, 1 per cache block. */
+ std::unique_ptr<uint8_t[]> dataBlks;
+
// Statistics
/**
* TODO: It would be good if these stats were acquired after warmup.
diff --git a/src/mem/cache/tags/base_set_assoc.cc
b/src/mem/cache/tags/base_set_assoc.cc
index 2475e6f..0ab806e 100644
--- a/src/mem/cache/tags/base_set_assoc.cc
+++ b/src/mem/cache/tags/base_set_assoc.cc
@@ -57,7 +57,6 @@
BaseSetAssoc::BaseSetAssoc(const Params *p)
:BaseTags(p), assoc(p->assoc), allocAssoc(p->assoc),
blks(p->size / p->block_size),
- dataBlks(new uint8_t[p->size]), // Allocate data storage in one big
chunk
numSets(p->size / (p->block_size * p->assoc)),
sequentialAccess(p->sequential_access),
sets(p->size / (p->block_size * p->assoc)),
diff --git a/src/mem/cache/tags/base_set_assoc.hh
b/src/mem/cache/tags/base_set_assoc.hh
index f7b386a..3bc275b 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -76,7 +76,6 @@
/** Typedef the set type used in this tag store. */
typedef CacheSet<CacheBlk> SetType;
-
protected:
/** The associativity of the cache. */
const unsigned assoc;
@@ -85,8 +84,6 @@
/** The cache blocks. */
std::vector<BlkType> blks;
- /** The data blocks, 1 per cache block. */
- std::unique_ptr<uint8_t[]> dataBlks;
/** The number of sets in the cache. */
const unsigned numSets;
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index a38d0bf..29e77b8 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -80,10 +80,12 @@
head->prev = nullptr;
head->next = &(blks[1]);
head->inCache = cacheMask;
+ head->data = &dataBlks[0];
tail->prev = &(blks[numBlocks-2]);
tail->next = nullptr;
tail->inCache = 0;
+ tail->data = &dataBlks[numBlocks-1];
unsigned index = (1 << 17) / blkSize;
unsigned j = 0;
@@ -100,6 +102,9 @@
blks[i].next = &(blks[i+1]);
blks[i].set = 0;
blks[i].way = i;
+
+ // Associate a data chunk to the block
+ blks[i].data = &dataBlks[blkSize*i];
}
assert(j == numCaches);
assert(index == numBlocks);
--
To view, visit https://gem5-review.googlesource.com/9302
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I10cbcf5afc3f8bc357eeb8b7cb46789dec47ba8b
Gerrit-Change-Number: 9302
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
