Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/9402

Change subject: sparc: Add some missing M5_FALLTHROUGHs and breaks.
......................................................................

sparc: Add some missing M5_FALLTHROUGHs and breaks.

These fix what I believe are some bugs, and also some gcc warnings.

Change-Id: I5fb2a1b2f0ef3643b25aaf0c29c096996ef98ec0
---
M src/arch/sparc/isa.cc
M src/arch/sparc/tlb.cc
M src/arch/sparc/ua2005.cc
3 files changed, 5 insertions(+), 0 deletions(-)



diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index f6b941e..3456029 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -480,6 +480,7 @@
         break;
       case MISCREG_HINTP:
         hintp = val;
+        break;
       case MISCREG_HTBA:
         htba = val;
         break;
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index f4564c6..49b353a 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -36,6 +36,7 @@
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/registers.hh"
 #include "base/bitfield.hh"
+#include "base/compiler.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
@@ -1155,6 +1156,7 @@
         break;
       case ASI_ITLB_DATA_ACCESS_REG:
         entry_insert = bits(va, 8,3);
+        M5_FALLTHROUGH;
       case ASI_ITLB_DATA_IN_REG:
         assert(entry_insert != -1 || mbits(va,10,9) == va);
         ta_insert = itb->tag_access;
@@ -1169,6 +1171,7 @@
         break;
       case ASI_DTLB_DATA_ACCESS_REG:
         entry_insert = bits(va, 8,3);
+        M5_FALLTHROUGH;
       case ASI_DTLB_DATA_IN_REG:
         assert(entry_insert != -1 || mbits(va,10,9) == va);
         ta_insert = tag_access;
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 274301b..d8af29b 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -137,6 +137,7 @@

       case MISCREG_PSTATE:
         setMiscRegNoEffect(miscReg, val);
+        break;

       case MISCREG_PIL:
         setMiscRegNoEffect(miscReg, val);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5fb2a1b2f0ef3643b25aaf0c29c096996ef98ec0
Gerrit-Change-Number: 9402
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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