Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/9502
to review the following change.
Change subject: arch-arm: Fix secure write of SCTLR when EL3 is AArch64
......................................................................
arch-arm: Fix secure write of SCTLR when EL3 is AArch64
MiscRegisters are not banked between secure and non-secure mode if EL3
is not implemented or if EL3 is using AArch64 (highestELIs64). In this
scenario a unique register is used and it is mapped to the NS version
(see snsBankedIndex implementation), so that a secure world read/write
should access the non secure storage.
Change-Id: Ica4182e3cdf4021d2bd1db23e477ce2bbf055926
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa.cc
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d0dccdd..899cda9 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -952,8 +952,14 @@
{
DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
scr = readMiscRegNoEffect(MISCREG_SCR);
- MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
- ? MISCREG_SCTLR_S :
MISCREG_SCTLR_NS;
+
+ MiscRegIndex sctlr_idx;
+ if (haveSecurity && !highestELIs64 && !scr.ns) {
+ sctlr_idx = MISCREG_SCTLR_S;
+ } else {
+ sctlr_idx = MISCREG_SCTLR_NS;
+ }
+
SCTLR sctlr = miscRegs[sctlr_idx];
SCTLR new_sctlr = newVal;
new_sctlr.nmfi = ((bool)sctlr.nmfi)
&& !haveVirtualization;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ica4182e3cdf4021d2bd1db23e477ce2bbf055926
Gerrit-Change-Number: 9502
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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