Hello Curtis Dunham,

I'd like you to do a code review. Please visit

    https://gem5-review.googlesource.com/9681

to review the following change.


Change subject: arch-arm: Fix mrc,mcr to cop14 disassemble
......................................................................

arch-arm: Fix mrc,mcr to cop14 disassemble

This patch fixes the disassemble for AArch32 mcr/mrc p14 instructions.

Change-Id: If5d7c2d7c726f040ae20053bf1d70f4405b34d0e
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Curtis Dunham <curtis.dun...@arm.com>
---
M src/arch/arm/isa/formats/misc.isa
M src/arch/arm/isa/insts/misc.isa
2 files changed, 8 insertions(+), 8 deletions(-)



diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index a9acc21..4f1960b 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -177,9 +177,9 @@
           default:
uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
             if (isRead) {
-                return new Mrc14(machInst, rt, (IntRegIndex)miscReg, iss);
+                return new Mrc14(machInst, rt, miscReg, iss);
             } else {
-                return new Mcr14(machInst, (IntRegIndex)miscReg, rt, iss);
+                return new Mcr14(machInst, miscReg, rt, iss);
             }
         }
     }
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 3aeee04..f1c6acf 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -875,11 +875,11 @@
     Dest = MiscOp1;
     '''

-    mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp",
+    mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp",
                              { "code": mrc14code,
                                "predicate_test": predicateTest }, [])
-    header_output += RegRegImmOpDeclare.subst(mrc14Iop)
-    decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
+    header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop)
+    decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop)
     exec_output += PredOpExecute.subst(mrc14Iop)


@@ -899,12 +899,12 @@
     }
     MiscDest = Op1;
     '''
-    mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp",
+    mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp",
                              { "code": mcr14code,
                                "predicate_test": predicateTest },
                                ["IsSerializeAfter","IsNonSpeculative"])
-    header_output += RegRegImmOpDeclare.subst(mcr14Iop)
-    decoder_output += RegRegImmOpConstructor.subst(mcr14Iop)
+    header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop)
+    decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop)
     exec_output += PredOpExecute.subst(mcr14Iop)

     mrc15code = '''

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If5d7c2d7c726f040ae20053bf1d70f4405b34d0e
Gerrit-Change-Number: 9681
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Curtis Dunham <curtis.dun...@arm.com>
Gerrit-MessageType: newchange
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