Robert Scheffel has uploaded this change for review. ( https://gem5-review.googlesource.com/9901

Change subject: arch-riscv: add bare metal example binary and script
......................................................................

arch-riscv: add bare metal example binary and script

This patch adds files, which can be used to test the bare metal full
system mode for riscv.

Change-Id: I5cccf0d6e5a2ad35d8b4d0bacbc6c5582c5dec47
---
A configs/example/riscv/fs_bare_metal.py
A configs/example/riscv/simple_system.py
A tests/test-progs/bare_metal/bin/riscv/bare_metal
A tests/test-progs/bare_metal/src/riscv/Makefile
A tests/test-progs/bare_metal/src/riscv/README.md
A tests/test-progs/bare_metal/src/riscv/link.ld
A tests/test-progs/bare_metal/src/riscv/main.c
A tests/test-progs/bare_metal/src/riscv/startup.S
8 files changed, 547 insertions(+), 0 deletions(-)



diff --git a/configs/example/riscv/fs_bare_metal.py b/configs/example/riscv/fs_bare_metal.py
new file mode 100644
index 0000000..c91c2ef
--- /dev/null
+++ b/configs/example/riscv/fs_bare_metal.py
@@ -0,0 +1,108 @@
+# Copyright (c) 2018 TU Dresden
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Robert Scheffel
+
+'''
+Full system script
+'''
+
+import argparse
+from simple_system import SimpleSystem
+
+import m5
+from m5.objects import *
+
+m5.util.addToPath('../..')
+from common import MemConfig
+
+cpu_types = {
+    'atomic': AtomicSimpleCPU,
+    'timing': TimingSimpleCPU,
+    'minor': MinorCPU
+}
+
+
+def create(args):
+    '''Create the system and configure it'''
+    cpu_class = cpu_types[args.cpu]
+    mem_mode = cpu_class.memory_mode()
+
+    system = SimpleSystem(cpu_class=cpu_class,
+                          wfgdb=args.wait_for_gdb,
+                          mem_mode=mem_mode,
+                          bootloader=args.binary)
+
+    # some required stuff
+    mem_type = 'DDR3_1600_8x8'
+    mem_channels = 1
+    args.mem_type = mem_type
+    args.mem_channels = mem_channels
+
+    MemConfig.config_mem(args, system)
+
+    system.connect()
+
+    return system
+
+
+def run():
+    '''Run the simulation'''
+    exit_event = m5.simulate()
+ print('Exiting because %s @ %d ' % (exit_event.getCause(), m5.curTick()))
+
+
+def main():
+    parser = argparse.ArgumentParser(epilog=__doc__)
+
+    parser.add_argument('-b',
+                        '--binary',
+                        type=str,
+                        default=None,
+                        required=True,
+                        help='The binary to run')
+    parser.add_argument('--cpu',
+                        type=str,
+                        default='atomic',
+                        help='CPU model to use')
+    parser.add_argument('-w',
+                        '--wait-for-gdb',
+                        action='store_true',
+                        help='Wait for remote gdb connection '
+                        'before starting simulation')
+
+    args = parser.parse_args()
+
+    root = Root(full_system=True)
+    root.system = create(args)
+
+    m5.instantiate()
+
+    run()
+
+
+if __name__ == '__m5_main__':
+    main()
diff --git a/configs/example/riscv/simple_system.py b/configs/example/riscv/simple_system.py
new file mode 100644
index 0000000..c637596
--- /dev/null
+++ b/configs/example/riscv/simple_system.py
@@ -0,0 +1,78 @@
+# Copyright (c) 2018 TU Dresden
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Robert Scheffel
+
+'''
+System definition.
+'''
+
+import m5
+from m5.objects import *
+
+
+class MemBus(SystemXBar):
+    badaddr_responder = BadAddr(warn_access="warn")
+    default = Self.badaddr_responder.pio
+
+
+class SimpleSystem(BareMetalRiscvSystem):
+    """
+    Simple system containing just CPU, bus and memory
+    """
+
+    def __init__(self, cpu_class, wfgdb, **kwargs):
+        super(SimpleSystem, self).__init__(**kwargs)
+
+        # create clock and voltage domain
+        # set to 100MHz clock frequency (like real hw board)
+        self.clk_domain = SrcClockDomain(clock='100MHz')
+        self.clk_domain.voltage_domain = VoltageDomain()
+
+        # create cpu and thread
+        # the interruptcontroller needs to be created as well
+        # tell the cpu if it shall wait until a gdb gets
+        # connected remotely or not
+        self.cpu = cpu_class()
+        self.cpu.createThreads()
+        self.cpu.createInterruptController()
+        self.cpu.wait_for_remote_gdb = wfgdb
+
+        # system memory bus
+        self.membus = MemBus()
+
+        # create mem_range
+        # for now start at 0x0
+        # take 3GB as size as it is a bit lower than 0xffffffff bytes
+        mem_start = Addr(0x00000000)
+        mem_size = '2GB'
+        self.mem_ranges = [AddrRange(start=mem_start, size=mem_size)]
+
+    def connect(self):
+        # connect cache ports of cpu to membus
+        # no caches -> connect directly to mem bus
+        self.cpu.connectAllPorts(self.membus)
+        self.system_port = self.membus.slave
diff --git a/tests/test-progs/bare_metal/bin/riscv/bare_metal b/tests/test-progs/bare_metal/bin/riscv/bare_metal
new file mode 100755
index 0000000..8130137
--- /dev/null
+++ b/tests/test-progs/bare_metal/bin/riscv/bare_metal
Binary files differ
diff --git a/tests/test-progs/bare_metal/src/riscv/Makefile b/tests/test-progs/bare_metal/src/riscv/Makefile
new file mode 100644
index 0000000..5efc23a
--- /dev/null
+++ b/tests/test-progs/bare_metal/src/riscv/Makefile
@@ -0,0 +1,63 @@
+# Copyright (c) 2018 TU Dresden
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Robert Scheffel
+
+TARGET=bare_metal
+
+SRC=$(wildcard *.c)
+ASM=$(wildcard *.S)
+OBJ=$(ASM:.S=.o) $(SRC:.c=.o)
+
+CC=riscv64-unknown-elf-gcc
+AS=riscv64-unknown-elf-as
+
+ASMFLAGS=-march=rv64gc
+CFLAGS=-std=c99 -O0 -Wall -Werror
+LDFLAGS=-T link.ld
+
+PREFIX=../../bin/riscv
+
+all : pre-build $(TARGET)
+
+pre-build :
+       -mkdir -p $(PREFIX)
+
+$(TARGET) : $(OBJ)
+       $(CC) $(LDFLAGS) $^ -o $(PREFIX)/$@
+
+%.o : %.S
+       $(AS) $(ASMFLAGS) $< -o $@
+
+%.o : %.c
+       $(CC) -c $(CFLAGS) $< -o $@
+
+.PHONY: clean clean_objects
+clean:
+       $(RM) -rf $(PREFIX) $(OBJ)
+
+clean_objects:
+       $(RM) -rf $(OBJ)
diff --git a/tests/test-progs/bare_metal/src/riscv/README.md b/tests/test-progs/bare_metal/src/riscv/README.md
new file mode 100644
index 0000000..54e2445
--- /dev/null
+++ b/tests/test-progs/bare_metal/src/riscv/README.md
@@ -0,0 +1,36 @@
+RISC-V bare metal Program
+=========================
+
+This directory contains code to build a very small and rudimentary bare metal application.
+
+
+Running the Application
+-----------------------
+
+To run the bare metal binary with the riscv bare metal fs script run
+```
+build/RISCV/gem5.opt configs/example/riscv/fs_bare_metal.py -b tests/test-progs/bare_metal/bin/riscv/bare_metal
+```
+For further information about arguments run
+```
+build/RISCV/gem5.opt configs/example/riscv/fs_bare_metal.py --help
+```
+
+
+Building the Application
+------------------------
+
+Assuming riscv64-unknown-elf-gcc and riscv64-unknown-elf-as are available in your PATH, you can just hit:
+```
+make
+```
+This will build an application called 'bare_metal' in the folder tests/test-progs/bare_metal/bin/riscv
+
+
+Source Code
+-----------
+
+Files in this directory:
+ * link.ld: A small linker script.
+ * startup.S: This file contains the startup code. The reset vector just jumps to the symbol 'startup', which lies in the text section. There all gp registers are zeroed. Afterwards the stack is initialised and control is given to the main function.
+ * main.c: Main function, that traps in a while loop.
diff --git a/tests/test-progs/bare_metal/src/riscv/link.ld b/tests/test-progs/bare_metal/src/riscv/link.ld
new file mode 100644
index 0000000..aa7db63
--- /dev/null
+++ b/tests/test-progs/bare_metal/src/riscv/link.ld
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2018 TU Dresden
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Robert Scheffel
+ */
+
+MEMORY {
+    resetVect : ORIGIN = 0x00000000, LENGTH = 0x00000010
+    irqVect :   ORIGIN = 0x00000010, LENGTH = 0x000000f0
+    mem :       ORIGIN = 0x00000100, LENGTH = 0x00017f00
+}
+
+ENTRY(_resetVect);
+
+SECTIONS {
+
+    __stack = ORIGIN(mem) + LENGTH(mem) - 4;
+
+    .resetVector : {
+        _resetVect = ABSOLUTE(.);
+        KEEP(*(.resetVect.text))
+    } > resetVect
+
+    .irqVector : {
+        *(.irq);
+    } > irqVect
+
+
+    .text :
+    {
+        *(.text)
+        *(.text.unlikely .text.*_unlikely .text.unlikely.*)
+        *(.text.exit .text.exit.*)
+        *(.text.startup .text.startup.*)
+        *(.text.hot .text.hot.*)
+        *(.stub .text.* .gnu.linkonce.t.*)
+        KEEP (*(SORT_NONE(.init)))
+        KEEP (*(SORT_NONE(.fini)))
+    } > mem
+
+
+    .rodata :
+    {
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        KEEP (*(.xt_except_table))
+        KEEP (*(.gcc_except_table))
+        *(.gnu.linkonce.e.*)
+        *(.gnu.version_r)
+        KEEP (*(.eh_frame))
+        /*  C++ constructor and destructor tables, properly ordered:  */
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*(.ctors))
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+        *(.gnu.linkonce.h.*)
+        *(.dynamic)
+        *(.gnu.version_d)
+    } > mem
+
+    .data :
+    {
+        *(.data .data.* .gnu.linkonce.d.*)
+        *(.data1)
+        PROVIDE( __global_pointer$ = . + (4K / 2) );
+        *(.sdata)
+        *(.sdata.*)
+        *(.gnu.linkonce.s.*)
+        *(.sdata2)
+        *(.sdata2.*)
+        *(.gnu.linkonce.s2.*)
+        _edata = .;
+    } > mem
+
+    .noinit (NOLOAD): ALIGN(4)
+    {
+        *(.noinit .noinit.*)
+    } > mem
+
+    .bss :
+    {
+        *(.dynbss)
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+        _end = .;
+    } > mem
+
+    /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+    /* DWARF 3 */
+    .debug_pubtypes 0 : { *(.debug_pubtypes) }
+    .debug_ranges   0 : { *(.debug_ranges) }
+    /* DWARF Extension.  */
+    .debug_macro    0 : { *(.debug_macro) }
+    .debug_addr     0 : { *(.debug_addr) }
+    .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+    /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+
+}
diff --git a/tests/test-progs/bare_metal/src/riscv/main.c b/tests/test-progs/bare_metal/src/riscv/main.c
new file mode 100644
index 0000000..444244b
--- /dev/null
+++ b/tests/test-progs/bare_metal/src/riscv/main.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2018 TU Dresden
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Robert Scheffel
+ */
+
+#include <stdio.h>
+
+int main()
+{
+    while (1);
+
+    return 0;
+}
\ No newline at end of file
diff --git a/tests/test-progs/bare_metal/src/riscv/startup.S b/tests/test-progs/bare_metal/src/riscv/startup.S
new file mode 100644
index 0000000..df1b31c
--- /dev/null
+++ b/tests/test-progs/bare_metal/src/riscv/startup.S
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018 TU Dresden
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Robert Scheffel
+ */
+
+    .section    .resetVect.text , "ax"
+reset_vect:
+    j       startup
+
+
+.section    .text
+    .type       main,@function
+startup:
+    li       x1, 0
+    li       x2, 0
+    li       x3, 0
+    li       x4, 0
+    li       x5, 0
+    li       x6, 0
+    li       x7, 0
+    li       x8, 0
+    li       x9, 0
+    li      x10, 0
+    li      x11, 0
+    li      x12, 0
+    li      x13, 0
+    li      x14, 0
+    li      x15, 0
+    li      x16, 0
+    li      x17, 0
+    li      x18, 0
+    li      x19, 0
+    li      x20, 0
+    li      x21, 0
+    li      x22, 0
+    li      x23, 0
+    li      x24, 0
+    li      x25, 0
+    li      x26, 0
+    li      x27, 0
+    li      x28, 0
+    li      x29, 0
+    li      x30, 0
+    li      x31, 0
+
+/* set stack pointer */
+    lui     sp, %hi(__stack)
+    addi    sp, sp, %lo(__stack)
+
+    j       main

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5cccf0d6e5a2ad35d8b4d0bacbc6c5582c5dec47
Gerrit-Change-Number: 9901
Gerrit-PatchSet: 1
Gerrit-Owner: Robert Scheffel <robert.scheff...@tu-dresden.de>
Gerrit-MessageType: newchange
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