Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/10063
to review the following change.
Change subject: arch-arm: Add ARMv8.1 TTBR1_EL2 register
......................................................................
arch-arm: Add ARMv8.1 TTBR1_EL2 register
This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg
table, but stil leaving it unimplemented (Accessing it through MSR/MRS
causes an exception)
Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 7f0e0f4..42d1b92 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1713,6 +1713,7 @@
case MISCREG_TTBR0_EL1:
case MISCREG_TTBR1_EL1:
case MISCREG_TTBR0_EL2:
+ case MISCREG_TTBR1_EL2:
case MISCREG_TTBR0_EL3:
getITBPtr(tc)->invalidateMiscReg();
getDTBPtr(tc)->invalidateMiscReg();
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index b5ae4ce..6615913 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1689,6 +1689,8 @@
switch (op2) {
case 0:
return MISCREG_TTBR0_EL2;
+ case 1:
+ return MISCREG_TTBR1_EL2;
case 2:
return MISCREG_TCR_EL2;
}
@@ -3519,6 +3521,8 @@
InitReg(MISCREG_TTBR0_EL2)
.hyp().mon()
.mapsTo(MISCREG_HTTBR);
+ InitReg(MISCREG_TTBR1_EL2)
+ .unimplemented();
InitReg(MISCREG_TCR_EL2)
.hyp().mon()
.mapsTo(MISCREG_HTCR);
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 9bca3d1..06d1a0d 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -666,14 +666,16 @@
MISCREG_CBAR_EL1, // 598
MISCREG_CONTEXTIDR_EL2, // 599
+ // Introduced in ARMv8.1
+ MISCREG_TTBR1_EL2, // 600
+
// These MISCREG_FREESLOT are available Misc Register
// slots for future registers to be implemented.
- MISCREG_FREESLOT_1, // 600
- MISCREG_FREESLOT_2, // 601
- MISCREG_FREESLOT_3, // 602
- MISCREG_FREESLOT_4, // 603
- MISCREG_FREESLOT_5, // 604
- MISCREG_FREESLOT_6, // 605
+ MISCREG_FREESLOT_1, // 601
+ MISCREG_FREESLOT_2, // 602
+ MISCREG_FREESLOT_3, // 603
+ MISCREG_FREESLOT_4, // 604
+ MISCREG_FREESLOT_5, // 605
// NUM_PHYS_MISCREGS specifies the number of actual physical
// registers, not considering the following pseudo-registers
@@ -1370,12 +1372,12 @@
"cbar_el1",
"contextidr_el2",
+ "ttbr1_el2",
"freeslot1",
"freeslot2",
"freeslot3",
"freeslot4",
"freeslot5",
- "freeslot6",
"num_phys_regs",
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b
Gerrit-Change-Number: 10063
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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