Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10061 )
Change subject: arch-arm: Change disassemble when MSR to UNKNOWN register
......................................................................
arch-arm: Change disassemble when MSR to UNKNOWN register
This patch changes the fault being thrown when MSR/MRS to an unknown
Misc register in AArch64. While previously the instruction was decoded
as an Unknown instruction (hence not printing any information), it is
now decoded as a FailUnimplemented and the unrecognized System register
numbers (CRn, op0...) are printed.
Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/10061
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa/formats/aarch64.isa
1 file changed, 8 insertions(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index 7752ba0..00bd077 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -369,7 +369,14 @@
}
// Check for invalid registers
if (miscReg == MISCREG_UNKNOWN) {
- return new Unknown64(machInst);
+ auto full_mnemonic =
+ csprintf("%s op0:%d op1:%d crn:%d crm:%d
op2:%d",
+ read ? "mrs" : "msr",
+ op0, op1, crn, crm, op2);
+
+ return new FailUnimplemented(read ? "mrs" : "msr",
+ machInst, full_mnemonic);
+
} else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
if (miscReg == MISCREG_NZCV) {
if (read)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc
Gerrit-Change-Number: 10061
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: merged
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