Matt Sinclair has uploaded this change for review. ( https://gem5-review.googlesource.com/10241

Change subject: arch-x86, arch-power: fix calls to bits and insertBits
......................................................................

arch-x86, arch-power: fix calls to bits and insertBits

The bits and insertBits assume the first bit is the larger bit and the last
bit is the smaller bit.  This commit fixes several X86 and Power calls to
these functions that incorrectly assumed that first was the smaller bit.  To
prevent this from happening in the future, I have added asserts in bits and insertBits to make sure the number of bits isn't negative.

Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01
---
M src/arch/power/isa/decoder.isa
M src/arch/x86/isa.cc
M src/base/bitfield.hh
3 files changed, 7 insertions(+), 5 deletions(-)



diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 71ef95b..6bc19ad 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -158,8 +158,8 @@
             508: cmpb({{
                 uint32_t val = 0;
                 for (int n = 0; n < 32; n += 8) {
-                    if(bits(Rs, n, n+7) == bits(Rb, n, n+7)) {
-                        val = insertBits(val, n, n+7, 0xff);
+                    if(bits(Rs, n+7, n) == bits(Rb, n+7, n)) {
+                        val = insertBits(val, n+7, n, 0xff);
                     }
                 }
                 Ra = val;
@@ -580,8 +580,8 @@
                         for (int i = 0; i < 8; ++i) {
                             if (bits(FLM, i) == 1) {
                                 int k = 4 * (i + (8 * (1 - W_FIELD)));
-                                FPSCR = insertBits(FPSCR, k, k + 3,
-                                                   bits(Fb_uq, k, k + 3));
+                                FPSCR = insertBits(FPSCR, k + 3, k,
+                                                   bits(Fb_uq, k + 3, k));
                             }
                         }
                     }
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 28c50f3..a866b95 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -145,7 +145,7 @@
     if (miscReg == MISCREG_FSW) {
         MiscReg fsw = regVal[MISCREG_FSW];
         MiscReg top = regVal[MISCREG_X87_TOP];
-        return insertBits(fsw, 11, 13, top);
+        return insertBits(fsw, 13, 11, top);
     }

     return readMiscRegNoEffect(miscReg);
diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 23c8b4b..f8d263e 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -71,6 +71,7 @@
 T
 bits(T val, int first, int last)
 {
+    assert((first - last) >= 0);
     int nbits = first - last + 1;
     return (val >> last) & mask(nbits);
 }
@@ -125,6 +126,7 @@
 insertBits(T val, int first, int last, B bit_val)
 {
     T t_bit_val = bit_val;
+    assert((first - last) >= 0);
     T bmask = mask(first - last + 1) << last;
     return ((t_bit_val << last) & bmask) | (val & ~bmask);
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01
Gerrit-Change-Number: 10241
Gerrit-PatchSet: 1
Gerrit-Owner: Matt Sinclair <mattdsincl...@gmail.com>
Gerrit-MessageType: newchange
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