Isaac Richter has uploaded this change for review. (
https://gem5-review.googlesource.com/10322
Change subject: cpu-o3: Add read barrier instruction types, implement them
in o3
......................................................................
cpu-o3: Add read barrier instruction types, implement them in o3
While looking at LFENCE operation (prior to
If89fcb552192326ab69a581f57d71c95cf5d90e7), I noticed that it was
basically a nop.
With this change, hopefully ISA instructions that are marked
IsReadBarrier will actually have an effect.
This is based on just copying what is used for stores, and may be
missing some corner cases, or have other bugs.
Change-Id: I1bb93b71b954a91edd4fb2d9187ee154430de19d
Signed-off-by: Isaac Richter <isaac.rich...@rochester.edu>
---
M src/cpu/base_dyn_inst.hh
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/mem_dep_unit_impl.hh
M src/cpu/static_inst.hh
6 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index ae408e3..00d2ca2 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -529,6 +529,7 @@
bool isSquashAfter() const { return staticInst->isSquashAfter(); }
bool isMemBarrier() const { return staticInst->isMemBarrier(); }
bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
+ bool isReadBarrier() const { return staticInst->isReadBarrier(); }
bool isNonSpeculative() const { return staticInst->isNonSpeculative();
}
bool isQuiesce() const { return staticInst->isQuiesce(); }
bool isIprAccess() const { return staticInst->isIprAccess(); }
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index d32493c..0f80fc9 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1153,6 +1153,7 @@
// think are possible.
assert(head_inst->isNonSpeculative() ||
head_inst->isStoreConditional()
|| head_inst->isMemBarrier() || head_inst->isWriteBarrier()
||
+ head_inst->isReadBarrier() ||
(head_inst->isLoad() && head_inst->strictlyOrdered()));
DPRINTF(Commit, "Encountered a barrier or non-speculative "
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 8270a71..95082ac 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1077,7 +1077,8 @@
}
toRename->iewInfo[tid].dispatchedToSQ++;
- } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
+ } else if (inst->isMemBarrier() || inst->isWriteBarrier() ||
+ inst->isReadBarrier()) {
// Same as non-speculative stores.
inst->setCanCommit();
instQueue.insertBarrier(inst);
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index f70f662..aae74f3 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1022,7 +1022,8 @@
memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
completeMemInst(completed_inst);
} else if (completed_inst->isMemBarrier() ||
- completed_inst->isWriteBarrier()) {
+ completed_inst->isWriteBarrier() ||
+ completed_inst->isReadBarrier()) {
memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
}
@@ -1270,7 +1271,8 @@
(!squashed_inst->isNonSpeculative() &&
!squashed_inst->isStoreConditional() &&
!squashed_inst->isMemBarrier() &&
- !squashed_inst->isWriteBarrier())) {
+ !squashed_inst->isWriteBarrier() &&
+ !squashed_inst->isReadBarrier())) {
for (int src_reg_idx = 0;
src_reg_idx < squashed_inst->numSrcRegs();
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh
b/src/cpu/o3/mem_dep_unit_impl.hh
index 376198f..994215e 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -319,6 +319,10 @@
storeBarrier = true;
storeBarrierSN = barr_sn;
DPRINTF(MemDepUnit, "Inserted a write barrier\n");
+ } else if (barr_inst->isReadBarrier()) {
+ loadBarrier = true;
+ loadBarrierSN = barr_sn;
+ DPRINTF(MemDepUnit, "Inserted a read barrier\n");
}
ThreadID tid = barr_inst->threadNumber;
@@ -444,6 +448,9 @@
} else if (inst->isWriteBarrier()) {
if (storeBarrierSN == barr_sn)
storeBarrier = false;
+ } else if (inst->isReadBarrier()) {
+ if (loadBarrierSN == barr_sn)
+ loadBarrier = false;
}
}
@@ -452,7 +459,8 @@
MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
{
// Only stores and barriers have dependents.
- if (!inst->isStore() && !inst->isMemBarrier()
&& !inst->isWriteBarrier()) {
+ if (!inst->isStore() && !inst->isMemBarrier()
&& !inst->isWriteBarrier()
+ && !inst->isReadBarrier()) {
return;
}
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 84b3525..7a904e2 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -173,6 +173,7 @@
bool isSquashAfter() const { return flags[IsSquashAfter]; }
bool isMemBarrier() const { return flags[IsMemBarrier]; }
bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
+ bool isReadBarrier() const { return flags[IsReadBarrier]; }
bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
bool isQuiesce() const { return flags[IsQuiesce]; }
bool isIprAccess() const { return flags[IsIprAccess]; }
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1bb93b71b954a91edd4fb2d9187ee154430de19d
Gerrit-Change-Number: 10322
Gerrit-PatchSet: 1
Gerrit-Owner: Isaac Richter <isaac.rich...@rochester.edu>
Gerrit-MessageType: newchange
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