Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10504 )
Change subject: arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as
NOP
......................................................................
arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP
In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.
Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/ArmISA.py
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/misc.isa
M src/arch/arm/miscregs.cc
6 files changed, 48 insertions(+), 6 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 7956570..78dd043 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2015-2016 ARM Limited
+# Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -111,3 +111,9 @@
# Reserved for future expansion
id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000,
"AArch64 Memory Model Feature Register 1")
+
+ # Any access (read/write) to an unimplemented
+ # Implementation Defined registers is not causing an Undefined
Instruction.
+ # It is rather executed as a NOP.
+ impdef_nop = Param.Bool(False,
+ "Any access to a MISCREG_IMPDEF_UNIMPL register is executed as
NOP")
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 296f8eb..a4e9c79 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -61,7 +61,8 @@
system(NULL),
_decoderFlavour(p->decoderFlavour),
_vecRegRenameMode(p->vecRegRenameMode),
- pmu(p->pmu)
+ pmu(p->pmu),
+ impdefAsNop(p->impdef_nop)
{
miscRegs[MISCREG_SCTLR_RST] = 0;
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index c8ae5c2..9158b62 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -90,6 +90,12 @@
bool haveLargeAsid64;
uint8_t physAddrRange64;
+ /**
+ * If true, accesses to IMPLEMENTATION DEFINED registers are
treated
+ * as NOP hence not causing UNDEFINED INSTRUCTION.
+ */
+ bool impdefAsNop;
+
/** MiscReg metadata **/
struct MiscRegLUTEntry {
uint32_t lower; // Lower half mapped to this register
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index 00bd077..722cd74 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -377,6 +377,20 @@
return new FailUnimplemented(read ? "mrs" : "msr",
machInst, full_mnemonic);
+ } else if (miscReg == MISCREG_IMPDEF_UNIMPL) {
+ auto full_mnemonic =
+ csprintf("%s op0:%d op1:%d crn:%d crm:%d
op2:%d",
+ read ? "mrs" : "msr",
+ op0, op1, crn, crm, op2);
+
+ if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
+ return new
WarnUnimplemented(read ? "mrs" : "msr",
+ machInst, full_mnemonic + " treated as
NOP");
+ } else {
+ return new
FailUnimplemented(read ? "mrs" : "msr",
+ machInst, full_mnemonic);
+ }
+
} else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
if (miscReg == MISCREG_NZCV) {
if (read)
diff --git a/src/arch/arm/isa/formats/misc.isa
b/src/arch/arm/isa/formats/misc.isa
index 4f1960b..7397417 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -220,10 +220,22 @@
csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s
unknown",
crn, opc1, crm, opc2, isRead ? "read" : "write"));
case MISCREG_IMPDEF_UNIMPL:
- return new McrMrcImplDefined(
- isRead ? "mrc implementation defined" :
- "mcr implementation defined",
- machInst, iss, MISCREG_IMPDEF_UNIMPL);
+
+ if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
+ auto mnemonic =
+ csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s",
+ crn, opc1, crm, opc2,
isRead ? "read" : "write");
+
+ return new WarnUnimplemented(
+ isRead ? "mrc implementation defined" :
+ "mcr implementation defined",
+ machInst, mnemonic + " treated as NOP");
+ } else {
+ return new McrMrcImplDefined(
+ isRead ? "mrc implementation defined" :
+ "mcr implementation defined",
+ machInst, iss, MISCREG_IMPDEF_UNIMPL);
+ }
case MISCREG_CP15ISB:
return new Isb(machInst, iss);
case MISCREG_CP15DSB:
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 31b3580..8dd56c7 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4008,6 +4008,9 @@
.unimplemented()
.warnNotFail();
InitReg(MISCREG_UNKNOWN);
+ InitReg(MISCREG_IMPDEF_UNIMPL)
+ .unimplemented()
+ .warnNotFail(impdefAsNop);
// Register mappings for some unimplemented registers:
// ESR_EL1 -> DFSR
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Gerrit-Change-Number: 10504
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: merged
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