Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/10501 )
Change subject: arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation
defined
......................................................................
arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation defined
In the AArch64 ISA, S3_<op1>_<Cn>_<Cm>_<op2> refers to a pool
of implementation defined registers, provided that reg numbers
are in the following range:
<op1> is in the range 0 - 7
<CRn> can take the values 11, 15
<CRm> is in the range 0 - 15
<op2> is in the range 0 - 7
Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10501
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/miscregs.cc
1 file changed, 7 insertions(+), 3 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index e1ddbf9..08e37bb 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -2082,9 +2082,12 @@
}
break;
}
- break;
+ M5_FALLTHROUGH;
+ default:
+ // S3_<op1>_11_<Cm>_<op2>
+ return MISCREG_IMPDEF_UNIMPL;
}
- break;
+ M5_UNREACHABLE;
case 12:
switch (op1) {
case 0:
@@ -2370,7 +2373,8 @@
}
break;
}
- break;
+ // S3_<op1>_15_<Cm>_<op2>
+ return MISCREG_IMPDEF_UNIMPL;
}
break;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50
Gerrit-Change-Number: 10501
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: merged
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