Andreas Sandberg has uploaded this change for review. ( https://gem5-review.googlesource.com/10805

Change subject: dev: Memory mapped device register utilities
......................................................................

dev: Memory mapped device register utilities

This change attempts to provide implementation of utilities which
could formalize memory mapped register definition. The utility in its
initial version provides basic register definition and memory
mapping. There is scope to enhance it by adding per register callback.

Change-Id: Ic06783b743a9d088fca813de2c4c95b6d5593eec
Signed-off-by: Rohit Kurup <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Signed-off-by: Andreas Sandberg <[email protected]>
---
M src/dev/SConscript
A src/dev/register_util.cc
A src/dev/register_util.hh
A src/dev/register_util_test.cc
4 files changed, 405 insertions(+), 0 deletions(-)



diff --git a/src/dev/SConscript b/src/dev/SConscript
index c9526c2..79ad50b 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -51,5 +51,10 @@
 Source('pixelpump.cc')
 Source('platform.cc')

+Source('register_util.cc')
+GTest('registertest',
+        'register_util_test.cc','../base/trace.cc','../base/debug.cc',
+        '../base/match.cc','../base/str.cc')
+
 DebugFlag('Intel8254Timer')
 DebugFlag('MC146818')
diff --git a/src/dev/register_util.cc b/src/dev/register_util.cc
new file mode 100644
index 0000000..a17939b
--- /dev/null
+++ b/src/dev/register_util.cc
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Rohit Kurup
+ */
+
+/** @file
+ * A Register library to implement device registers
+ * in address space
+ */
+
+#include "dev/register_util.hh"
+
+template<typename DataType>
+DataType
+RegisterBlock<DataType>::readReg(Addr offset)
+{
+    DataType value = 0xDEADBEEF;
+    auto search = register_map.find(offset);
+
+    // Found register
+    if (search != register_map.end()) {
+        value = ((*search).second)->getRegister();
+        if (dbgFlag.status()) {
+            Trace::getDebugLogger()->dprintf(
+                curTick(), mname, "RegRd %s:0x%x:0x%lx\n",
+                ((*search).second)->name(), offset, value);
+        }
+    } else  {
+        warn("Unimplemented Register 0x%x\n", offset);
+    }
+
+    return value;
+}
+
+template<typename DataType>
+void
+RegisterBlock<DataType>::writeReg(Addr offset, DataType value)
+{
+    auto search = register_map.find(offset);
+
+    // Found a register
+    if (search != register_map.end())  {
+        ((*search).second)->setRegister(value);
+        if (dbgFlag.status()) {
+            Trace::getDebugLogger()->dprintf(
+                curTick(), mname,
+                "RegWr %s:0x%x:0x%lx\n",
+                ((*search).second)->name(), offset, value);
+        }
+    } else  {
+        warn("Unimplemented Register 0x%x\n", offset);
+    }
+}
+
+template<typename DataType>
+void
+RegisterBlock<DataType>::serialize(CheckpointOut &cp) const
+{
+    for (auto it : register_map) {
+        DataType value = (*it.second).getRegister();
+        paramOut(cp, (*it.second).name(), value);
+    }
+}
+
+template<typename DataType>
+void
+RegisterBlock<DataType>::unserialize(CheckpointIn &cp)
+{
+    for (auto it : register_map) {
+        DataType value = 0;
+
+        paramIn(cp, (*it.second).name(), value);
+        (*it.second).setRegisterNoEffect(value);
+    }
+}
+
+template<typename DataType>
+void
+RegisterBlock<DataType>::addToBlock(
+    std::pair<Addr,RegisterBase<DataType> *> entry)
+{
+    register_map.insert(entry);
+}
+
+
+/**
+ * Dummy declaration needed for template since we kept declaration and
+ * implementation of template in separate files. This helps compiler
+ * generate the needed code.
+ */
+template class RegisterBlock<uint32_t>;
+template class RegisterBlock<uint64_t>;
diff --git a/src/dev/register_util.hh b/src/dev/register_util.hh
new file mode 100644
index 0000000..d59eace
--- /dev/null
+++ b/src/dev/register_util.hh
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Rohit Kurup
+ */
+
+/** @file
+ * A Register library to implement device registers
+ * in address space
+ */
+
+#ifndef __DEV_REGISTER_UTIL_HH__
+#define __DEV_REGISTER_UTIL_HH__
+
+#include <map>
+
+#include "base/bitunion.hh"
+#include "base/debug.hh"
+#include "base/logging.hh"
+#include "base/trace.hh"
+#include "base/types.hh"
+#include "sim/serialize.hh"
+
+/**
+ * Abstract Register Base class defining access methods for a
+ * arbitrary width register
+ */
+template<typename DataType>
+class RegisterBase
+{
+  public:
+    virtual void setRegister(const DataType &) = 0;
+    virtual void setRegisterNoEffect(const DataType &) = 0;
+    virtual DataType getRegister() const = 0;
+    virtual std::string name() const = 0;
+};
+
+/**
+ * Models a block containing memory mapped registers
+ * TBD per Register callback to avoid massive switch statements
+ * in the callback
+ */
+template<typename DataType>
+class RegisterBlock : public Serializable
+{
+    std::string mname;
+    Debug::SimpleFlag &dbgFlag;
+
+  protected:
+    /**
+     * Registers indexed against the address offset
+     */
+    std::map<Addr, RegisterBase<DataType> *> register_map;
+
+  public:
+    RegisterBlock(Debug::SimpleFlag &dbgFlag, std::string mname)
+        : mname(mname), dbgFlag(dbgFlag) { }
+
+    /**
+     * Interface supposed to be used by Master
+     */
+    DataType readReg(Addr offset);
+    void writeReg(Addr offset, DataType value);
+    void serialize(CheckpointOut &cp) const override;
+    void unserialize(CheckpointIn &cp) override;
+    void addToBlock(std::pair<Addr, RegisterBase<DataType> *> entry);
+};
+
+
+/**
+ * Determine the underlying storage for the Register
+ */
+template<typename __DataType>
+struct RegisterStorageType
+{
+    typedef typename std::conditional<
+        std::is_integral<__DataType>::value,
+        __DataType, BitUnionBaseType<__DataType>
+        >::type type;
+};
+
+/**
+ * Class representing a memory mapped register
+ *
+ * BaseType is the BaseClass type which will hold the register, it
+ * should be derived from RegisterBlock<>.
+ *
+ * __Datatype is the underlying storage type and could be a complex
+ * type like BitUnion
+ *
+ * Operator -> provides BitUnion like semantics (e.g., uint32_t,
+ * uint64_t)
+ */
+template<typename BaseType, typename __DataType>
+class Register : public RegisterBase<
+    typename RegisterStorageType<__DataType>::type>
+{
+    typedef typename RegisterStorageType<__DataType>::type DataType;
+    std::string reg_name;
+    __DataType reg_data;
+    BaseType *reg_block;
+
+    std::function<void(void)> rdCallback;
+    std::function<void(void)> wrCallback;
+
+    Register()
+    {
+    }
+
+  public:
+
+    Register(BaseType *_parent, Addr offset,
+             std::string name, DataType reset_val = 0x0)
+        : reg_name(name), reg_data(reset_val), reg_block(_parent)
+    {
+        reg_block->addToBlock({offset, this});
+    }
+
+    std::string name() const override { return reg_name; }
+
+    void
+    setRegister(const DataType &val) override
+    {
+        reg_data = val;
+        if (wrCallback) wrCallback();
+    }
+
+ void setRegisterNoEffect(const DataType &val) override { reg_data = val; }
+
+    DataType
+    getRegister() const override
+    {
+        if (rdCallback)
+            rdCallback();
+        return reg_data;
+    }
+
+
+    Register<BaseType,__DataType> &
+    operator=(const DataType &val)
+    {
+        reg_data = val;
+        return *this;
+    }
+
+    operator DataType() { return reg_data; }
+
+    __DataType *operator->() { return &reg_data; }
+
+    void setReadCB(std::function<void(void)> rd_cb) { rdCallback = rd_cb; }
+ void setWriteCB(std::function<void(void)> wr_cb) { wrCallback = wr_cb; }
+
+};
+
+#endif // __DEV_REGISTER_UTIL_HH__
diff --git a/src/dev/register_util_test.cc b/src/dev/register_util_test.cc
new file mode 100644
index 0000000..a4b290f
--- /dev/null
+++ b/src/dev/register_util_test.cc
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Rohit Kurup
+ */
+
+/** @file
+ *
+ */
+
+#include <gtest/gtest.h>
+
+#include "base/bitunion.hh"
+#include "dev/register_util.hh"
+#include "sim/serialize.hh"
+
+BitUnion32(MyType)
+   Bitfield<31,16> f2;
+   Bitfield<15,0> f1;
+EndBitUnion(MyType)
+
+namespace Debug
+{
+    SimpleFlag MyModule("MyModule", "Debug Flag for test module");
+};
+
+
+class MyModule : public RegisterBlock<uint32_t>
+{
+  public :
+    Register<MyModule,MyType> myReg;
+
+    MyModule()
+        : RegisterBlock(Debug::MyModule, "MyModule"),
+          myReg(this,0x0,"myReg",0x0)
+    {
+        myReg.setReadCB([this]{this->myRegRdCB();});
+        myReg.setWriteCB([this]{this->myRegWrCB();});
+        myReg = 0xAAAABBBB;
+    }
+
+    ~MyModule() {}
+
+    void myRegRdCB() {}
+
+    void myRegWrCB() {}
+};
+
+TEST(RegisterUtilTest, CompileTest)
+{
+    EXPECT_EQ(0x1, 0x1);
+}
+

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ic06783b743a9d088fca813de2c4c95b6d5593eec
Gerrit-Change-Number: 10805
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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