Andreas Sandberg has submitted this change and it was merged. (
https://gem5-review.googlesource.com/11589 )
Change subject: arch-arm: Fix incorrect t{0,1}sz field in TTBCR
......................................................................
arch-arm: Fix incorrect t{0,1}sz field in TTBCR
The t0sz and t1sz fields in TTBCR only are only three bits wide unlike
aarch64 which has a 6-bit wide field. The higher bits of the
aarch64-equivalent should be treated as RES0.
Change-Id: I60df73105c34500c0348a44a491c117e9b28f18f
Signed-off-by: Andreas Sandberg <[email protected]>
Reviewed-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/11589
Maintainer: Giacomo Travaglini <[email protected]>
---
M src/arch/arm/miscregs.hh
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index f9386b4..1a88c92 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1722,13 +1722,13 @@
Bitfield<4> pd0;
Bitfield<5> pd1;
// Long-descriptor translation table format
- Bitfield<5, 0> t0sz;
+ Bitfield<2, 0> t0sz;
Bitfield<7> epd0;
Bitfield<9, 8> irgn0;
Bitfield<11, 10> orgn0;
Bitfield<13, 12> sh0;
Bitfield<14> tg0;
- Bitfield<21, 16> t1sz;
+ Bitfield<18, 16> t1sz;
Bitfield<22> a1;
Bitfield<23> epd1;
Bitfield<25, 24> irgn1;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I60df73105c34500c0348a44a491c117e9b28f18f
Gerrit-Change-Number: 11589
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: merged
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