Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/11592
to review the following change.
Change subject: arch-arm: Introduce ARMv8.1 Virtual Timer System Registers
......................................................................
arch-arm: Introduce ARMv8.1 Virtual Timer System Registers
Adding CNTHV_CTL_EL2, CNTHV_CVAL_EL2, CNTHV_TVAL_EL2 System Registers
into the decode tree. They are currently implemented as a generic timer
and produces a warning if accessed.
Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
3 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9b17927..c701cc3 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -644,6 +644,9 @@
return 0; // bits [63:0] RES0 (reserved for future use)
// Generic Timer registers
+ case MISCREG_CNTHV_CTL_EL2:
+ case MISCREG_CNTHV_CVAL_EL2:
+ case MISCREG_CNTHV_TVAL_EL2:
case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
@@ -1913,6 +1916,9 @@
break;
// Generic Timer registers
+ case MISCREG_CNTHV_CTL_EL2:
+ case MISCREG_CNTHV_CVAL_EL2:
+ case MISCREG_CNTHV_TVAL_EL2:
case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index cab5a70..bbd5347 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -2331,6 +2331,16 @@
return MISCREG_CNTHP_CVAL_EL2;
}
break;
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_CNTHV_TVAL_EL2;
+ case 1:
+ return MISCREG_CNTHV_CTL_EL2;
+ case 2:
+ return MISCREG_CNTHV_CVAL_EL2;
+ }
+ break;
}
break;
case 7:
@@ -4018,6 +4028,12 @@
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CONTEXTIDR_EL2)
.mon().hyp();
+ InitReg(MISCREG_CNTHV_CTL_EL2)
+ .mon().hyp();
+ InitReg(MISCREG_CNTHV_CVAL_EL2)
+ .mon().hyp();
+ InitReg(MISCREG_CNTHV_TVAL_EL2)
+ .mon().hyp();
// Dummy registers
InitReg(MISCREG_NOP)
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 4567964..c1d5efa 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -668,14 +668,14 @@
// Introduced in ARMv8.1
MISCREG_TTBR1_EL2, // 600
+ MISCREG_CNTHV_CTL_EL2, // 601
+ MISCREG_CNTHV_CVAL_EL2, // 602
+ MISCREG_CNTHV_TVAL_EL2, // 603
// These MISCREG_FREESLOT are available Misc Register
// slots for future registers to be implemented.
- MISCREG_FREESLOT_1, // 601
- MISCREG_FREESLOT_2, // 602
- MISCREG_FREESLOT_3, // 603
- MISCREG_FREESLOT_4, // 604
- MISCREG_FREESLOT_5, // 605
+ MISCREG_FREESLOT_1, // 604
+ MISCREG_FREESLOT_2, // 605
// NUM_PHYS_MISCREGS specifies the number of actual physical
// registers, not considering the following pseudo-registers
@@ -1385,11 +1385,11 @@
"contextidr_el2",
"ttbr1_el2",
+ "cnthv_ctl_el2",
+ "cnthv_cval_el2",
+ "cnthv_tval_el2",
"freeslot1",
"freeslot2",
- "freeslot3",
- "freeslot4",
- "freeslot5",
"num_phys_regs",
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504
Gerrit-Change-Number: 11592
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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