Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/11591 )
Change subject: arch-arm: Introduce RAS System Registers
......................................................................
arch-arm: Introduce RAS System Registers
Adding RAS Extension System Registers into the decode tree. They are
currently unimplemented and produce a warning (not failure) if accessed.
Change-Id: I4baeded822c9582a2cb9d5277409b029eb00a962
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/11591
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
2 files changed, 98 insertions(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 89caa14..cab5a70 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1857,6 +1857,34 @@
return MISCREG_ESR_EL1;
}
break;
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_ERRIDR_EL1;
+ case 1:
+ return MISCREG_ERRSELR_EL1;
+ }
+ break;
+ case 4:
+ switch (op2) {
+ case 0:
+ return MISCREG_ERXFR_EL1;
+ case 1:
+ return MISCREG_ERXCTLR_EL1;
+ case 2:
+ return MISCREG_ERXSTATUS_EL1;
+ case 3:
+ return MISCREG_ERXADDR_EL1;
+ }
+ break;
+ case 5:
+ switch (op2) {
+ case 0:
+ return MISCREG_ERXMISC0_EL1;
+ case 1:
+ return MISCREG_ERXMISC1_EL1;
+ }
+ break;
}
break;
case 4:
@@ -1879,6 +1907,8 @@
switch (op2) {
case 0:
return MISCREG_ESR_EL2;
+ case 3:
+ return MISCREG_VSESR_EL2;
}
break;
case 3:
@@ -2104,6 +2134,8 @@
switch (op2) {
case 0:
return MISCREG_ISR_EL1;
+ case 1:
+ return MISCREG_DISR_EL1;
}
break;
}
@@ -2118,6 +2150,12 @@
return MISCREG_RVBAR_EL2;
}
break;
+ case 1:
+ switch (op2) {
+ case 1:
+ return MISCREG_VDISR_EL2;
+ }
+ break;
}
break;
case 6:
@@ -3997,6 +4035,41 @@
.unimplemented()
.warnNotFail(impdefAsNop);
+ // RAS extension (unimplemented)
+ InitReg(MISCREG_ERRIDR_EL1)
+ .unimplemented()
+ .warnNotFail();
+ InitReg(MISCREG_ERRSELR_EL1)
+ .unimplemented()
+ .warnNotFail();
+ InitReg(MISCREG_ERXFR_EL1)
+ .unimplemented()
+ .warnNotFail();
+ InitReg(MISCREG_ERXCTLR_EL1)
+ .unimplemented()
+ .warnNotFail();
+ InitReg(MISCREG_ERXSTATUS_EL1)
+ .unimplemented()
+ .warnNotFail();
+ InitReg(MISCREG_ERXADDR_EL1)
+ .unimplemented()
+ .warnNotFail();
+ InitReg(MISCREG_ERXMISC0_EL1)
+ .unimplemented()
+ .warnNotFail();
+ InitReg(MISCREG_ERXMISC1_EL1)
+ .unimplemented()
+ .warnNotFail();
+ InitReg(MISCREG_DISR_EL1)
+ .unimplemented()
+ .warnNotFail();
+ InitReg(MISCREG_VSESR_EL2)
+ .unimplemented()
+ .warnNotFail();
+ InitReg(MISCREG_VDISR_EL2)
+ .unimplemented()
+ .warnNotFail();
+
// Register mappings for some unimplemented registers:
// ESR_EL1 -> DFSR
// RMR_EL1 -> RMR
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 1a88c92..4567964 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -696,6 +696,19 @@
// either UNDEFINED or hypervisor trap exception.
MISCREG_IMPDEF_UNIMPL,
+ // RAS extension (unimplemented)
+ MISCREG_ERRIDR_EL1,
+ MISCREG_ERRSELR_EL1,
+ MISCREG_ERXFR_EL1,
+ MISCREG_ERXCTLR_EL1,
+ MISCREG_ERXSTATUS_EL1,
+ MISCREG_ERXADDR_EL1,
+ MISCREG_ERXMISC0_EL1,
+ MISCREG_ERXMISC1_EL1,
+ MISCREG_DISR_EL1,
+ MISCREG_VSESR_EL2,
+ MISCREG_VDISR_EL2,
+
// Total number of Misc Registers: Physical + Dummy
NUM_MISCREGS
};
@@ -1386,7 +1399,18 @@
"cp14_unimpl",
"cp15_unimpl",
"unknown",
- "impl_defined"
+ "impl_defined",
+ "erridr_el1",
+ "errselr_el1",
+ "erxfr_el1",
+ "erxctlr_el1",
+ "erxstatus_el1",
+ "erxaddr_el1",
+ "erxmisc0_el1",
+ "erxmisc1_el1",
+ "disr_el1",
+ "vsesr_el2",
+ "vdisr_el2",
};
static_assert(sizeof(miscRegName) / sizeof(*miscRegName) ==
NUM_MISCREGS,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I4baeded822c9582a2cb9d5277409b029eb00a962
Gerrit-Change-Number: 11591
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: merged
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