Hello, I ran fs mode both with NonCachingSimpleCPU and AtomicSimpleCPU, however NCSC failed to restore the first checkpoint, as it couldn't serialize one of the variables. Further exploration led me to the following output from stats.txt (the number of committed instructions is correctly set as 10 for both cpu types):
GEM5_OPT --redirect-stdout --redirect-stderr --outdir=OUT_DIR PATH_TO/fs.py --cpu-type=NonCachingSimpleCPU -n 1 --mem-size=8GB --sys-clock=4GHz --cpu-clock=4GHz --kernel=KERNEL_PATH --disk-image=IMG_PATH --checkpoint-dir=CPT_DIR --checkpoint-restore=10 --at-instruction --take-checkpoints=9 --checkpoint-at-end sim_seconds 0.004051 # Number of seconds simulated sim_ticks 4051187500 # Number of ticks simulated final_tick 13226883926750 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 87045 # Simulator instruction rate (inst/s) host_op_rate 159212 # Simulator op (including micro ops) rate (op/s) host_tick_rate 46751461 # Simulator tick rate (ticks/s) host_mem_usage 9242984 # Number of bytes of host memory used host_seconds 86.65 # Real time elapsed on the host sim_insts 7542728 # Number of instructions simulated sim_ops 13796291 # Number of ops (including micro ops) simulated GEM5_OPT --redirect-stdout --redirect-stderr --outdir=OUT_DIR PATH_TO/fs.py --cpu-type=AtomicSimpleCPU -n 1 --mem-size=8GB --sys-clock=4GHz --cpu-clock=4GHz --kernel=KERNEL_PATH --disk-image=IMG_PATH --checkpoint-dir=CPT_DIR --checkpoint-restore=10 --at-instruction --take-checkpoints=9 --checkpoint-at-end sim_seconds 0.000000 # Number of seconds simulated sim_ticks 8250 # Number of ticks simulated final_tick 13222832747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 0 # Simulator instruction rate (inst/s) host_op_rate 0 # Simulator op (including micro ops) rate (op/s) host_tick_rate 55 # Simulator tick rate (ticks/s) host_mem_usage 9006272 # Number of bytes of host memory used host_seconds 149.86 # Real time elapsed on the host sim_insts 10 # Number of instructions simulated sim_ops 30 # Number of ops (including micro ops) simulated Unless the run command should be modified when changing between these cpu types, I believe there is a bug on the code, as there shouldn't be that many simulated instructions on NonCachingSimpleCPU. If I'm not mistaken (I don't have easy access to the dir that compiled this), this Gem5 version dates to 07/13/18. Is anyone working on/familiar with this part of the code able to confirm this? Regards,Daniel _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
