Nikos Nikoleris has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/12908
Change subject: tests: Add a test for the cache write streaming
optimizations
......................................................................
tests: Add a test for the cache write streaming optimizations
The purpose of this regression test is to make sure that optimizations
for write streaming access patterns in the classic memory system
(caches) work as expected.
This test instantiates a simple system, with a traffic generator, a L1
cache and a L2 cache and a simple memory. The traffic generator
performs writes which the L1 cache coalesces and turns into whole-line
writes (WriteLineReq). The effect of write coalescing can be seen in
the stats where the number of ReadExReq accesses in the L2 cache
should be really small, as most requests to the L2 should be
InvalidateReq.
Change-Id: Ic50e771d1597bf2ba899c9615c593c37ae47f2e1
---
A tests/configs/write-streaming.py
A tests/quick/se/52.write-streaming/ref/null/none/write-streaming/stats.txt
A tests/quick/se/52.write-streaming/test.py
M tests/testing/tests.py
4 files changed, 435 insertions(+), 0 deletions(-)
diff --git a/tests/configs/write-streaming.py
b/tests/configs/write-streaming.py
new file mode 100644
index 0000000..a48dad9
--- /dev/null
+++ b/tests/configs/write-streaming.py
@@ -0,0 +1,94 @@
+# Copyright (c) 2018 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2015 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+# Nikos Nikoleris
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/')
+from common.Caches import *
+
+# system simulated
+system = System(physmem = SimpleMemory(),
+ membus = SystemXBar())
+
+system.tgen = PyTrafficGen()
+
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain =
system.voltage_domain)
+
+system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
+system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB',
assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+
+# connect l2c to membus
+system.l2c.mem_side = system.membus.slave
+
+system.tgen.l1c = L1Cache(size = '32kB', assoc = 4,
+ write_allocator = WriteAllocator())
+system.tgen.port = system.tgen.l1c.cpu_side
+system.tgen.l1c.mem_side = system.toL2Bus.slave
+
+system.system_port = system.membus.slave
+
+# connect memory to membus
+system.physmem.port = system.membus.master
+
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'timing'
+
+m5.instantiate()
+
+def trace():
+ yield system.tgen.createLinear(
+ 10000000000, 0, 16777216, 8, 500, 1000, 0, 0)
+ yield system.tgen.createExit(0)
+
+system.tgen.start(trace())
+
+exit_event = m5.simulate()
+print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())
+sys.exit(0)
diff --git
a/tests/quick/se/52.write-streaming/ref/null/none/write-streaming/stats.txt
b/tests/quick/se/52.write-streaming/ref/null/none/write-streaming/stats.txt
new file mode 100644
index 0000000..8fc5433
--- /dev/null
+++
b/tests/quick/se/52.write-streaming/ref/null/none/write-streaming/stats.txt
@@ -0,0 +1,288 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.010000
+sim_ticks 10000000000
+final_tick 10000000000
+sim_freq 1000000000000
+host_tick_rate 2363704259
+host_mem_usage 227656
+host_seconds 4.23
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 10000000000
+system.physmem.bytes_read::tgen 448
+system.physmem.bytes_read::total 448
+system.physmem.bytes_written::writebacks 35760320
+system.physmem.bytes_written::total 35760320
+system.physmem.num_reads::tgen 7
+system.physmem.num_reads::total 7
+system.physmem.num_writes::writebacks 558755
+system.physmem.num_writes::total 558755
+system.physmem.bw_read::tgen 44800
+system.physmem.bw_read::total 44800
+system.physmem.bw_write::writebacks 3576032000
+system.physmem.bw_write::total 3576032000
+system.physmem.bw_total::writebacks 3576032000
+system.physmem.bw_total::tgen 44800
+system.physmem.bw_total::total 3576076800
+system.pwrStateResidencyTicks::UNDEFINED 10000000000
+system.cpu_clk_domain.clock 500
+system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 10000000000
+system.l2c.tags.tagsinuse 1023.043428
+system.l2c.tags.total_refs 559788
+system.l2c.tags.sampled_refs 559788
+system.l2c.tags.avg_refs 1
+system.l2c.tags.warmup_cycle 54000
+system.l2c.tags.occ_blocks::writebacks 1023.030647
+system.l2c.tags.occ_blocks::tgen 0.012781
+system.l2c.tags.occ_percent::writebacks 0.999053
+system.l2c.tags.occ_percent::tgen 0.000012
+system.l2c.tags.occ_percent::total 0.999066
+system.l2c.tags.occ_task_id_blocks::1024 1024
+system.l2c.tags.age_task_id_blocks_1024::0 556
+system.l2c.tags.age_task_id_blocks_1024::1 468
+system.l2c.tags.occ_task_id_percent::1024 1
+system.l2c.tags.tag_accesses 9516524
+system.l2c.tags.data_accesses 9516524
+system.l2c.pwrStateResidencyTicks::UNDEFINED 10000000000
+system.l2c.WritebackDirty_hits::writebacks 559781
+system.l2c.WritebackDirty_hits::total 559781
+system.l2c.ReadExReq_misses::tgen 7
+system.l2c.ReadExReq_misses::total 7
+system.l2c.InvalidateReq_misses::tgen 559804
+system.l2c.InvalidateReq_misses::total 559804
+system.l2c.demand_misses::tgen 7
+system.l2c.demand_misses::total 7
+system.l2c.overall_misses::tgen 7
+system.l2c.overall_misses::total 7
+system.l2c.ReadExReq_miss_latency::tgen 436500
+system.l2c.ReadExReq_miss_latency::total 436500
+system.l2c.demand_miss_latency::tgen 436500
+system.l2c.demand_miss_latency::total 436500
+system.l2c.overall_miss_latency::tgen 436500
+system.l2c.overall_miss_latency::total 436500
+system.l2c.WritebackDirty_accesses::writebacks 559781
+system.l2c.WritebackDirty_accesses::total 559781
+system.l2c.ReadExReq_accesses::tgen 7
+system.l2c.ReadExReq_accesses::total 7
+system.l2c.InvalidateReq_accesses::tgen 559804
+system.l2c.InvalidateReq_accesses::total 559804
+system.l2c.demand_accesses::tgen 7
+system.l2c.demand_accesses::total 7
+system.l2c.overall_accesses::tgen 7
+system.l2c.overall_accesses::total 7
+system.l2c.ReadExReq_miss_rate::tgen 1
+system.l2c.ReadExReq_miss_rate::total 1
+system.l2c.InvalidateReq_miss_rate::tgen 1
+system.l2c.InvalidateReq_miss_rate::total 1
+system.l2c.demand_miss_rate::tgen 1
+system.l2c.demand_miss_rate::total 1
+system.l2c.overall_miss_rate::tgen 1
+system.l2c.overall_miss_rate::total 1
+system.l2c.ReadExReq_avg_miss_latency::tgen 62357.142857
+system.l2c.ReadExReq_avg_miss_latency::total 62357.142857
+system.l2c.demand_avg_miss_latency::tgen 62357.142857
+system.l2c.demand_avg_miss_latency::total 62357.142857
+system.l2c.overall_avg_miss_latency::tgen 62357.142857
+system.l2c.overall_avg_miss_latency::total 62357.142857
+system.l2c.blocked_cycles::no_mshrs 0
+system.l2c.blocked_cycles::no_targets 0
+system.l2c.blocked::no_mshrs 0
+system.l2c.blocked::no_targets 0
+system.l2c.avg_blocked_cycles::no_mshrs nan
+system.l2c.avg_blocked_cycles::no_targets nan
+system.l2c.writebacks::writebacks 558757
+system.l2c.writebacks::total 558757
+system.l2c.ReadExReq_mshr_misses::tgen 7
+system.l2c.ReadExReq_mshr_misses::total 7
+system.l2c.InvalidateReq_mshr_misses::tgen 559804
+system.l2c.InvalidateReq_mshr_misses::total 559804
+system.l2c.demand_mshr_misses::tgen 7
+system.l2c.demand_mshr_misses::total 7
+system.l2c.overall_mshr_misses::tgen 7
+system.l2c.overall_mshr_misses::total 7
+system.l2c.ReadExReq_mshr_miss_latency::tgen 366500
+system.l2c.ReadExReq_mshr_miss_latency::total 366500
+system.l2c.InvalidateReq_mshr_miss_latency::tgen 12042394756
+system.l2c.InvalidateReq_mshr_miss_latency::total 12042394756
+system.l2c.demand_mshr_miss_latency::tgen 366500
+system.l2c.demand_mshr_miss_latency::total 366500
+system.l2c.overall_mshr_miss_latency::tgen 366500
+system.l2c.overall_mshr_miss_latency::total 366500
+system.l2c.ReadExReq_mshr_miss_rate::tgen 1
+system.l2c.ReadExReq_mshr_miss_rate::total 1
+system.l2c.InvalidateReq_mshr_miss_rate::tgen 1
+system.l2c.InvalidateReq_mshr_miss_rate::total 1
+system.l2c.demand_mshr_miss_rate::tgen 1
+system.l2c.demand_mshr_miss_rate::total 1
+system.l2c.overall_mshr_miss_rate::tgen 1
+system.l2c.overall_mshr_miss_rate::total 1
+system.l2c.ReadExReq_avg_mshr_miss_latency::tgen 52357.142857
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 52357.142857
+system.l2c.InvalidateReq_avg_mshr_miss_latency::tgen 21511.805482
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 21511.805482
+system.l2c.demand_avg_mshr_miss_latency::tgen 52357.142857
+system.l2c.demand_avg_mshr_miss_latency::total 52357.142857
+system.l2c.overall_avg_mshr_miss_latency::tgen 52357.142857
+system.l2c.overall_avg_mshr_miss_latency::total 52357.142857
+system.l2c.replacements 558764
+system.membus.snoop_filter.tot_requests 1118568
+system.membus.snoop_filter.hit_single_requests 558755
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 10000000000
+system.membus.trans_dist::WritebackDirty 558755
+system.membus.trans_dist::ReadExReq 7
+system.membus.trans_dist::ReadExResp 7
+system.membus.trans_dist::InvalidateReq 559804
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port
1118573
+system.membus.pkt_count::total 1118573
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port
35760768
+system.membus.pkt_size::total 35760768
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 559813
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 559813 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 559813
+system.membus.reqLayer0.occupancy 3483436708
+system.membus.reqLayer0.utilization 34.8
+system.membus.respLayer0.occupancy 35000
+system.membus.respLayer0.utilization 0.0
+system.tgen.pwrStateResidencyTicks::UNDEFINED 10000000000
+system.tgen.numSuppressed 0
+system.tgen.numPackets 4478706
+system.tgen.numRetries 247434
+system.tgen.retryTicks 6826830170
+system.tgen.l1c.tags.pwrStateResidencyTicks::UNDEFINED 10000000000
+system.tgen.l1c.tags.tagsinuse 14.948471
+system.tgen.l1c.tags.total_refs 246
+system.tgen.l1c.tags.sampled_refs 29
+system.tgen.l1c.tags.avg_refs 8.482759
+system.tgen.l1c.tags.warmup_cycle 64500
+system.tgen.l1c.tags.occ_blocks::tgen 14.948471
+system.tgen.l1c.tags.occ_percent::tgen 0.029196
+system.tgen.l1c.tags.occ_percent::total 0.029196
+system.tgen.l1c.tags.occ_task_id_blocks::1024 29
+system.tgen.l1c.tags.age_task_id_blocks_1024::2 10
+system.tgen.l1c.tags.age_task_id_blocks_1024::3 19
+system.tgen.l1c.tags.occ_task_id_percent::1024 0.056641
+system.tgen.l1c.tags.tag_accesses 17914853
+system.tgen.l1c.tags.data_accesses 17914853
+system.tgen.l1c.pwrStateResidencyTicks::UNDEFINED 10000000000
+system.tgen.l1c.WriteReq_hits::tgen 217
+system.tgen.l1c.WriteReq_hits::total 217
+system.tgen.l1c.demand_hits::tgen 217
+system.tgen.l1c.demand_hits::total 217
+system.tgen.l1c.overall_hits::tgen 217
+system.tgen.l1c.overall_hits::total 217
+system.tgen.l1c.WriteReq_misses::tgen 4478489
+system.tgen.l1c.WriteReq_misses::total 4478489
+system.tgen.l1c.demand_misses::tgen 4478489
+system.tgen.l1c.demand_misses::total 4478489
+system.tgen.l1c.overall_misses::tgen 4478489
+system.tgen.l1c.overall_misses::total 4478489
+system.tgen.l1c.WriteReq_miss_latency::tgen 236926837807
+system.tgen.l1c.WriteReq_miss_latency::total 236926837807
+system.tgen.l1c.demand_miss_latency::tgen 236926837807
+system.tgen.l1c.demand_miss_latency::total 236926837807
+system.tgen.l1c.overall_miss_latency::tgen 236926837807
+system.tgen.l1c.overall_miss_latency::total 236926837807
+system.tgen.l1c.WriteReq_accesses::tgen 4478706
+system.tgen.l1c.WriteReq_accesses::total 4478706
+system.tgen.l1c.demand_accesses::tgen 4478706
+system.tgen.l1c.demand_accesses::total 4478706
+system.tgen.l1c.overall_accesses::tgen 4478706
+system.tgen.l1c.overall_accesses::total 4478706
+system.tgen.l1c.WriteReq_miss_rate::tgen 0.999952
+system.tgen.l1c.WriteReq_miss_rate::total 0.999952
+system.tgen.l1c.demand_miss_rate::tgen 0.999952
+system.tgen.l1c.demand_miss_rate::total 0.999952
+system.tgen.l1c.overall_miss_rate::tgen 0.999952
+system.tgen.l1c.overall_miss_rate::total 0.999952
+system.tgen.l1c.WriteReq_avg_miss_latency::tgen 52903.297922
+system.tgen.l1c.WriteReq_avg_miss_latency::total 52903.297922
+system.tgen.l1c.demand_avg_miss_latency::tgen 52903.297922
+system.tgen.l1c.demand_avg_miss_latency::total 52903.297922
+system.tgen.l1c.overall_avg_miss_latency::tgen 52903.297922
+system.tgen.l1c.overall_avg_miss_latency::total 52903.297922
+system.tgen.l1c.blocked_cycles::no_mshrs 7005431
+system.tgen.l1c.blocked_cycles::no_targets 0
+system.tgen.l1c.blocked::no_mshrs 247438
+system.tgen.l1c.blocked::no_targets 0
+system.tgen.l1c.avg_blocked_cycles::no_mshrs 28.311864
+system.tgen.l1c.avg_blocked_cycles::no_targets nan
+system.tgen.l1c.writebacks::writebacks 559782
+system.tgen.l1c.writebacks::total 559782
+system.tgen.l1c.WriteReq_mshr_hits::tgen 3918677
+system.tgen.l1c.WriteReq_mshr_hits::total 3918677
+system.tgen.l1c.demand_mshr_hits::tgen 3918677
+system.tgen.l1c.demand_mshr_hits::total 3918677
+system.tgen.l1c.overall_mshr_hits::tgen 3918677
+system.tgen.l1c.overall_mshr_hits::total 3918677
+system.tgen.l1c.WriteReq_mshr_misses::tgen 559812
+system.tgen.l1c.WriteReq_mshr_misses::total 559812
+system.tgen.l1c.demand_mshr_misses::tgen 559812
+system.tgen.l1c.demand_mshr_misses::total 559812
+system.tgen.l1c.overall_mshr_misses::tgen 559812
+system.tgen.l1c.overall_mshr_misses::total 559812
+system.tgen.l1c.WriteReq_mshr_miss_latency::tgen 35526462125
+system.tgen.l1c.WriteReq_mshr_miss_latency::total 35526462125
+system.tgen.l1c.demand_mshr_miss_latency::tgen 35526462125
+system.tgen.l1c.demand_mshr_miss_latency::total 35526462125
+system.tgen.l1c.overall_mshr_miss_latency::tgen 35526462125
+system.tgen.l1c.overall_mshr_miss_latency::total 35526462125
+system.tgen.l1c.WriteReq_mshr_miss_rate::tgen 0.124994
+system.tgen.l1c.WriteReq_mshr_miss_rate::total 0.124994
+system.tgen.l1c.demand_mshr_miss_rate::tgen 0.124994
+system.tgen.l1c.demand_mshr_miss_rate::total 0.124994
+system.tgen.l1c.overall_mshr_miss_rate::tgen 0.124994
+system.tgen.l1c.overall_mshr_miss_rate::total 0.124994
+system.tgen.l1c.WriteReq_avg_mshr_miss_latency::tgen 63461.415841
+system.tgen.l1c.WriteReq_avg_mshr_miss_latency::total 63461.415841
+system.tgen.l1c.demand_avg_mshr_miss_latency::tgen 63461.415841
+system.tgen.l1c.demand_avg_mshr_miss_latency::total 63461.415841
+system.tgen.l1c.overall_avg_mshr_miss_latency::tgen 63461.415841
+system.tgen.l1c.overall_avg_mshr_miss_latency::total 63461.415841
+system.tgen.l1c.replacements 0
+system.toL2Bus.snoop_filter.tot_requests 1119592
+system.toL2Bus.snoop_filter.hit_single_requests 559781
+system.toL2Bus.snoop_filter.hit_multi_requests 0
+system.toL2Bus.snoop_filter.tot_snoops 7
+system.toL2Bus.snoop_filter.hit_single_snoops 7
+system.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 10000000000
+system.toL2Bus.trans_dist::WritebackDirty 1118538
+system.toL2Bus.trans_dist::CleanEvict 7
+system.toL2Bus.trans_dist::ReadExReq 7
+system.toL2Bus.trans_dist::ReadExResp 7
+system.toL2Bus.trans_dist::InvalidateReq 559804
+system.toL2Bus.trans_dist::InvalidateResp 559804
+system.toL2Bus.pkt_count_system.tgen.l1c.mem_side::system.l2c.cpu_side
1679403
+system.toL2Bus.pkt_size_system.tgen.l1c.mem_side::system.l2c.cpu_side
35826432
+system.toL2Bus.snoops 558764
+system.toL2Bus.snoopTraffic 35760448
+system.toL2Bus.snoop_fanout::samples 1118575
+system.toL2Bus.snoop_fanout::mean 0.000006
+system.toL2Bus.snoop_fanout::stdev 0.002502
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.toL2Bus.snoop_fanout::0 1118568 100.00% 100.00%
+system.toL2Bus.snoop_fanout::1 7 0.00% 100.00%
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.toL2Bus.snoop_fanout::min_value 0
+system.toL2Bus.snoop_fanout::max_value 1
+system.toL2Bus.snoop_fanout::total 1118575
+system.toL2Bus.reqLayer0.occupancy 1141338390
+system.toL2Bus.reqLayer0.utilization 11.4
+system.toL2Bus.respLayer0.occupancy 279912500
+system.toL2Bus.respLayer0.utilization 2.8
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/52.write-streaming/test.py
b/tests/quick/se/52.write-streaming/test.py
new file mode 100644
index 0000000..b45ec96
--- /dev/null
+++ b/tests/quick/se/52.write-streaming/test.py
@@ -0,0 +1,52 @@
+# Copyright (c) 2018 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nikos Nikoleris
+
+#
+# The purpose of this regression test is to make sure that
+# optimizations for write streaming access patterns in the classic
+# memory system (caches) work as expected.
+#
+# This test instantiates a simple system, with a traffic generator, a
+# L1 cache and a L2 cache and a simple memory. The traffic generator
+# performs writes which the L1 cache coalesces and turns into
+# whole-line writes (WriteLineReq). The effect of write coalescing can
+# be seen in the stats where the number of ReadExReq accesses in the
+# L2 cache should be really small, as most requests to the L2 should
+# be InvalidateReq.
+#
+
+maxtick = 10000000000
diff --git a/tests/testing/tests.py b/tests/testing/tests.py
index 123d3b1..3360f96 100755
--- a/tests/testing/tests.py
+++ b/tests/testing/tests.py
@@ -158,6 +158,7 @@
'tgen-simple-mem',
'tgen-dram-ctrl',
'dram-lowp',
+ 'write-streaming',
'learning-gem5-p1-simple',
'learning-gem5-p1-two-level',
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ic50e771d1597bf2ba899c9615c593c37ae47f2e1
Gerrit-Change-Number: 12908
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris <[email protected]>
Gerrit-MessageType: newchange
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