Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/12948
Change subject: dev-arm: Enable FIQ signaling for Group0 interrupts in GICv2
......................................................................
dev-arm: Enable FIQ signaling for Group0 interrupts in GICv2
Change-Id: Iafaf26344a26eade60c08dd2c0d716af14d9b328
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
2 files changed, 50 insertions(+), 4 deletions(-)
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 355ee73..6b4d77e 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -364,7 +364,7 @@
ctx, iar.ack_id, iar.cpu_id, iar);
cpuHighestInt[ctx] = SPURIOUS_INT;
updateIntState(-1);
- platform->intrctrl->clear(ctx, ArmISA::INT_IRQ, 0);
+ clearInt(ctx, active_int);
return iar;
} else {
return SPURIOUS_INT;
@@ -795,7 +795,7 @@
if (isLevelSensitive(cpu, prev_highest)) {
DPRINTF(Interrupt, "Clear IRQ for cpu%d\n", cpu);
- platform->intrctrl->clear(cpu, ArmISA::INT_IRQ, 0);
+ clearInt(cpu, prev_highest);
}
continue;
}
@@ -809,7 +809,12 @@
DPRINTF(Interrupt, "Posting interrupt %d to cpu%d\n",
highest_int,
cpu);
- postInt(cpu, curTick() + intLatency);
+
+ if (isFiq(cpu, highest_int)) {
+ postFiq(cpu, curTick() + intLatency);
+ } else {
+ postInt(cpu, curTick() + intLatency);
+ }
}
}
}
@@ -895,6 +900,16 @@
}
void
+GicV2::clearInt(ContextID ctx, uint32_t int_num)
+{
+ if (isFiq(ctx, int_num)) {
+ platform->intrctrl->clear(ctx, ArmISA::INT_FIQ, 0);
+ } else {
+ platform->intrctrl->clear(ctx, ArmISA::INT_IRQ, 0);
+ }
+}
+
+void
GicV2::postInt(uint32_t cpu, Tick when)
{
if (!(postIntEvent[cpu]->scheduled())) {
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 4f30b00..c9c1a47 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -334,7 +334,35 @@
}
}
- /** CPU enabled */
+ bool isGroup0(ContextID ctx, uint32_t int_num) {
+ const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num));
+ return bits(group_reg, intNumToBit(int_num));
+ }
+
+ /**
+ * This method checks if an interrupt ID must be signaled or has been
+ * signaled as a FIQ to the cpu. It does that by reading:
+ *
+ * 1) GICD_IGROUPR: controls if the interrupt is part of group0 or
+ * group1. Only group0 interrupts can be signaled as FIQs.
+ *
+ * 2) GICC_CTLR.FIQEn: controls whether the CPU interface signals
Group 0
+ * interrupts to a target processor using the FIQ or the IRQ signal
+ */
+ bool isFiq(ContextID ctx, uint32_t int_num) {
+ const bool is_group0 = isGroup0(ctx, int_num);
+ const bool use_fiq = cpuControl[ctx].fiqEn;
+
+ if (is_group0 && use_fiq) {
+ return true;
+ } else {
+ return false;
+ }
+ }
+
+ /** CPU enabled:
+ * Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set
+ */
bool cpuEnabled(ContextID ctx) const {
return cpuControl[ctx].enableGrp0 ||
cpuControl[ctx].enableGrp1;
@@ -393,6 +421,9 @@
int intNumToWord(int num) const { return num >> 5; }
int intNumToBit(int num) const { return num % 32; }
+ /** Clears a cpu IRQ or FIQ signal */
+ void clearInt(ContextID ctx, uint32_t int_num);
+
/**
* Post an interrupt to a CPU with a delay
*/
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iafaf26344a26eade60c08dd2c0d716af14d9b328
Gerrit-Change-Number: 12948
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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