Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13066
to review the following change.
Change subject: arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
......................................................................
arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
This patch implements AArch64 Memory Model Feature Register 2
(from ARMv8.2)
Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/ArmISA.py
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/utility.cc
6 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 78dd043..52c42cb 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -111,6 +111,8 @@
# Reserved for future expansion
id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000,
"AArch64 Memory Model Feature Register 1")
+ id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
+ "AArch64 Memory Model Feature Register 2")
# Any access (read/write) to an unimplemented
# Implementation Defined registers is not causing an Undefined
Instruction.
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a42495d..508c3bf 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -319,6 +319,7 @@
miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
+ miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
miscRegs[MISCREG_ID_DFR0_EL1] =
(p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
@@ -1002,6 +1003,7 @@
case MISCREG_ID_AA64ISAR1_EL1:
case MISCREG_ID_AA64MMFR0_EL1:
case MISCREG_ID_AA64MMFR1_EL1:
+ case MISCREG_ID_AA64MMFR2_EL1:
case MISCREG_ID_AA64PFR0_EL1:
case MISCREG_ID_AA64PFR1_EL1:
// ID registers are constants.
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index bbd5347..07123bd 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1539,7 +1539,9 @@
return MISCREG_ID_AA64MMFR0_EL1;
case 1:
return MISCREG_ID_AA64MMFR1_EL1;
- case 2 ... 7:
+ case 2:
+ return MISCREG_ID_AA64MMFR2_EL1;
+ case 3 ... 7:
return MISCREG_RAZ;
}
break;
@@ -3504,6 +3506,8 @@
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64MMFR1_EL1)
.allPrivileges().exceptUserMode().writes(0);
+ InitReg(MISCREG_ID_AA64MMFR2_EL1)
+ .allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CCSIDR_EL1)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CLIDR_EL1)
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 08d6abf..ab3fc8f 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -672,10 +672,10 @@
MISCREG_CNTHV_CVAL_EL2, // 602
MISCREG_CNTHV_TVAL_EL2, // 603
+ MISCREG_ID_AA64MMFR2_EL1, // 604
// These MISCREG_FREESLOT are available Misc Register
// slots for future registers to be implemented.
- MISCREG_FREESLOT_1, // 604
- MISCREG_FREESLOT_2, // 605
+ MISCREG_FREESLOT_1, // 605
// NUM_PHYS_MISCREGS specifies the number of actual physical
// registers, not considering the following pseudo-registers
@@ -1388,7 +1388,7 @@
"cnthv_ctl_el2",
"cnthv_cval_el2",
"cnthv_tval_el2",
- "freeslot1",
+ "id_aa64mmfr2_el1",
"freeslot2",
"num_phys_regs",
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index 68738cb..67bbb14 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -415,6 +415,7 @@
{ "id_aa64isar1_el1", MISCREG_ID_AA64ISAR1_EL1 },
{ "id_aa64mmfr0_el1", MISCREG_ID_AA64MMFR0_EL1 },
{ "id_aa64mmfr1_el1", MISCREG_ID_AA64MMFR1_EL1 },
+ { "id_aa64mmfr2_el1", MISCREG_ID_AA64MMFR2_EL1 },
{ "ccsidr_el1", MISCREG_CCSIDR_EL1 },
{ "clidr_el1", MISCREG_CLIDR_EL1 },
{ "aidr_el1", MISCREG_AIDR_EL1 },
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index dec85ef..e642250 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -750,6 +750,7 @@
case MISCREG_ID_AA64ISAR1_EL1:
case MISCREG_ID_AA64MMFR0_EL1:
case MISCREG_ID_AA64MMFR1_EL1:
+ case MISCREG_ID_AA64MMFR2_EL1:
case MISCREG_ID_AA64AFR0_EL1:
case MISCREG_ID_AA64AFR1_EL1:
assert(isRead);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13066
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf
Gerrit-Change-Number: 13066
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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