Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/12947 )
Change subject: dev-arm: Create postFiq events for GICv2
......................................................................
dev-arm: Create postFiq events for GICv2
GICv2 is signaling IRQs only to the CPU. This patch is adding the
capability of scheduling FIQs.
Change-Id: I395afc83eb8d58cfd32cd93372bcb6f804364ef5
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/12947
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
---
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
2 files changed, 28 insertions(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 01358b7..7bbc89e 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -88,6 +88,9 @@
postIntEvent[x] =
new EventFunctionWrapper([this, x]{ postDelayedInt(x); },
"Post Interrupt to CPU");
+ postFiqEvent[x] =
+ new EventFunctionWrapper([this, x]{ postDelayedFiq(x); },
+ "Post FIQ to CPU");
}
DPRINTF(Interrupt, "cpuEnabled[0]=%d cpuEnabled[1]=%d\n",
cpuEnabled(0),
cpuEnabled(1));
@@ -97,8 +100,10 @@
GicV2::~GicV2()
{
- for (int x = 0; x < CPU_MAX; x++)
+ for (int x = 0; x < CPU_MAX; x++) {
delete postIntEvent[x];
+ delete postFiqEvent[x];
+ }
}
Tick
@@ -915,6 +920,25 @@
signalDrainDone();
}
+void
+GicV2::postFiq(uint32_t cpu, Tick when)
+{
+ if (!(postFiqEvent[cpu]->scheduled())) {
+ ++pendingDelayedInterrupts;
+ eventq->schedule(postFiqEvent[cpu], when);
+ }
+}
+
+void
+GicV2::postDelayedFiq(uint32_t cpu)
+{
+ platform->intrctrl->post(cpu, ArmISA::INT_FIQ, 0);
+ --pendingDelayedInterrupts;
+ assert(pendingDelayedInterrupts >= 0);
+ if (pendingDelayedInterrupts == 0)
+ signalDrainDone();
+}
+
DrainState
GicV2::drain()
{
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 4ca2f38..4f30b00 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -397,13 +397,16 @@
* Post an interrupt to a CPU with a delay
*/
void postInt(uint32_t cpu, Tick when);
+ void postFiq(uint32_t cpu, Tick when);
/**
* Deliver a delayed interrupt to the target CPU
*/
void postDelayedInt(uint32_t cpu);
+ void postDelayedFiq(uint32_t cpu);
EventFunctionWrapper *postIntEvent[CPU_MAX];
+ EventFunctionWrapper *postFiqEvent[CPU_MAX];
int pendingDelayedInterrupts;
public:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I395afc83eb8d58cfd32cd93372bcb6f804364ef5
Gerrit-Change-Number: 12947
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Ciro Santilli <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-MessageType: merged
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