Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/12884 )
Change subject: sim-se: Different HWCAP for ArmProcess32/64
......................................................................
sim-se: Different HWCAP for ArmProcess32/64
AArch32 and AArch64 have different HWCAP flags in Linux, but we are
currently using AArch32 HWCAP flags to initialize the aux vector of both
AArch32 and AArch64 binaries.
This patch also fixes a bug that was introduced by running in SE mode a
target binary compiled with glibc > 2.18. Using AArch32 flags
resulted on CPUID flag being set for AArch64. This incorrectly tells
libc that emulation of the midr_el1 is supported.
In FullSystem this might work, but since we are in Syscall Emulation
there is no OS behind emulating the mrs midr_el1 instruction.
By separating AArch32 flags from AArch64 flags we are turning off the
CPUID hwcap flag in SE mode.
Change-Id: I9f651957ba9d19dc2bc06606de070c6586f0f9fa
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/12884
Reviewed-by: Brandon Potter <[email protected]>
Maintainer: Brandon Potter <[email protected]>
---
M src/arch/arm/process.cc
M src/arch/arm/process.hh
2 files changed, 85 insertions(+), 37 deletions(-)
Approvals:
Brandon Potter: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 0c1d18b..0dfd393 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012 ARM Limited
+ * Copyright (c) 2010, 2012, 2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -142,6 +142,71 @@
}
}
+uint32_t
+ArmProcess32::armHwcapImpl() const
+{
+ enum ArmCpuFeature {
+ Arm_Swp = 1 << 0,
+ Arm_Half = 1 << 1,
+ Arm_Thumb = 1 << 2,
+ Arm_26Bit = 1 << 3,
+ Arm_FastMult = 1 << 4,
+ Arm_Fpa = 1 << 5,
+ Arm_Vfp = 1 << 6,
+ Arm_Edsp = 1 << 7,
+ Arm_Java = 1 << 8,
+ Arm_Iwmmxt = 1 << 9,
+ Arm_Crunch = 1 << 10,
+ Arm_ThumbEE = 1 << 11,
+ Arm_Neon = 1 << 12,
+ Arm_Vfpv3 = 1 << 13,
+ Arm_Vfpv3d16 = 1 << 14
+ };
+
+ return Arm_Swp | Arm_Half | Arm_Thumb | Arm_FastMult |
+ Arm_Vfp | Arm_Edsp | Arm_ThumbEE | Arm_Neon |
+ Arm_Vfpv3 | Arm_Vfpv3d16;
+}
+
+uint32_t
+ArmProcess64::armHwcapImpl() const
+{
+ // In order to know what these flags mean, please refer to Linux
+ // /Documentation/arm64/elf_hwcaps.txt text file.
+ enum ArmCpuFeature {
+ Arm_Fp = 1 << 0,
+ Arm_Asimd = 1 << 1,
+ Arm_Evtstrm = 1 << 2,
+ Arm_Aes = 1 << 3,
+ Arm_Pmull = 1 << 4,
+ Arm_Sha1 = 1 << 5,
+ Arm_Sha2 = 1 << 6,
+ Arm_Crc32 = 1 << 7,
+ Arm_Atomics = 1 << 8,
+ Arm_Fphp = 1 << 9,
+ Arm_Asimdhp = 1 << 10,
+ Arm_Cpuid = 1 << 11,
+ Arm_Asimdrdm = 1 << 12,
+ Arm_Jscvt = 1 << 13,
+ Arm_Fcma = 1 << 14,
+ Arm_Lrcpc = 1 << 15,
+ Arm_Dcpop = 1 << 16,
+ Arm_Sha3 = 1 << 17,
+ Arm_Sm3 = 1 << 18,
+ Arm_Sm4 = 1 << 19,
+ Arm_Asimddp = 1 << 20,
+ Arm_Sha512 = 1 << 21,
+ Arm_Sve = 1 << 22,
+ Arm_Asimdfhm = 1 << 23,
+ Arm_Dit = 1 << 24,
+ Arm_Uscat = 1 << 25,
+ Arm_Ilrcpc = 1 << 26,
+ Arm_Flagm = 1 << 27
+ };
+
+ return Arm_Fp | Arm_Asimd | Arm_Evtstrm | Arm_Crc32;
+}
+
template <class IntType>
void
ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
@@ -166,47 +231,13 @@
// load object file into target memory
objFile->loadSections(initVirtMem);
- enum ArmCpuFeature {
- Arm_Swp = 1 << 0,
- Arm_Half = 1 << 1,
- Arm_Thumb = 1 << 2,
- Arm_26Bit = 1 << 3,
- Arm_FastMult = 1 << 4,
- Arm_Fpa = 1 << 5,
- Arm_Vfp = 1 << 6,
- Arm_Edsp = 1 << 7,
- Arm_Java = 1 << 8,
- Arm_Iwmmxt = 1 << 9,
- Arm_Crunch = 1 << 10,
- Arm_ThumbEE = 1 << 11,
- Arm_Neon = 1 << 12,
- Arm_Vfpv3 = 1 << 13,
- Arm_Vfpv3d16 = 1 << 14
- };
-
//Setup the auxilliary vectors. These will already have endian
conversion.
//Auxilliary vectors are loaded only for elf formatted executables.
ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
if (elfObject) {
if (objFile->getOpSys() == ObjectFile::Linux) {
- IntType features =
- Arm_Swp |
- Arm_Half |
- Arm_Thumb |
-// Arm_26Bit |
- Arm_FastMult |
-// Arm_Fpa |
- Arm_Vfp |
- Arm_Edsp |
-// Arm_Java |
-// Arm_Iwmmxt |
-// Arm_Crunch |
- Arm_ThumbEE |
- Arm_Neon |
- Arm_Vfpv3 |
- Arm_Vfpv3d16 |
- 0;
+ IntType features = armHwcap<IntType>();
//Bits which describe the system hardware capabilities
//XXX Figure out what these should be
diff --git a/src/arch/arm/process.hh b/src/arch/arm/process.hh
index f4f0874..a6f46c1 100644
--- a/src/arch/arm/process.hh
+++ b/src/arch/arm/process.hh
@@ -1,5 +1,5 @@
/*
-* Copyright (c) 2012 ARM Limited
+* Copyright (c) 2012, 2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -61,6 +61,17 @@
ObjectFile::Arch _arch);
template<class IntType>
void argsInit(int pageSize, ArmISA::IntRegIndex spIndex);
+
+ template<class IntType>
+ IntType armHwcap() const
+ {
+ return static_cast<IntType>(armHwcapImpl());
+ }
+
+ /**
+ * AT_HWCAP is 32-bit wide on AArch64 as well so we can
+ * safely return an uint32_t */
+ virtual uint32_t armHwcapImpl() const = 0;
};
class ArmProcess32 : public ArmProcess
@@ -71,6 +82,9 @@
void initState();
+ /** AArch32 AT_HWCAP */
+ uint32_t armHwcapImpl() const override;
+
public:
ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
@@ -87,6 +101,9 @@
void initState();
+ /** AArch64 AT_HWCAP */
+ uint32_t armHwcapImpl() const override;
+
public:
ArmISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9f651957ba9d19dc2bc06606de070c6586f0f9fa
Gerrit-Change-Number: 12884
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Brandon Potter <[email protected]>
Gerrit-Reviewer: Ciro Santilli <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: merged
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