Hi Gabe, I have been thinking along similar lines. I think I would prefer wrapping the registers in a struct and/or union to make the access size explicit. Floats are a bit annoying though since x86 would, ideally, need-80 bit registers. I think there might be a similar issue for integer registers once 128-bit RISCV ISA has been defined. The CPU models probably wouldn't need to worry about the contents of the structs though, so it should be possible to optimise at compile time if someone decides to only compile a subset of the ISAs.
In general, I think this would be a good direction since it would make gem5 more modular. Cheers, Andreas On 12/10/2018 11:58, Gabe Black wrote:
Hi folks. I was digging around in gem5 today, and thinking about the ISA dependencies of the ThreadContext class. Some of those stem from the fact that many of the functions in that class are for accessing registers, and each ISA has different types defined for integer, floating point, and "misc" (control) registers. It seems to me that at least for the functions that access those registers, we could standardize on a generic type for all the ISAs. That would be similar to how the Addr type is the same for all ISAs, specifically a uint64_t. That type is sufficient for all the ISAs we support, although it may not always be necessary. Similarly, I think we could make the universal type for integer and control registers, a uint64_t, and floating point registers doubles. The actual type consumed by instructions could be down converted to something smaller if necessary with no loss of information. Thoughts? Gabe _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
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