Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13539 )
Change subject: arch: Get rid of the unused type AnyReg.
......................................................................
arch: Get rid of the unused type AnyReg.
This type is defined for all the ISAs but isn't used by anything.
Change-Id: I659a0c5abc7883d82fedd1cac2cd103612d315c8
Reviewed-on: https://gem5-review.googlesource.com/c/13539
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/alpha/registers.hh
M src/arch/arm/registers.hh
M src/arch/mips/registers.hh
M src/arch/power/registers.hh
M src/arch/sparc/registers.hh
M src/arch/x86/registers.hh
6 files changed, 0 insertions(+), 40 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 151ea7d..53ade47 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -66,13 +66,6 @@
// This has to be one to prevent warnings that are treated as errors
constexpr unsigned NumVecRegs = 1;
-union AnyReg
-{
- IntReg intreg;
- FloatReg fpreg;
- MiscReg ctrlreg;
-};
-
enum MiscRegIndex
{
MISCREG_FPCR = NumInternalProcRegs,
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 0a617e4..e7defd1 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -119,13 +119,6 @@
const int SyscallPseudoReturnReg = ReturnValueReg;
const int SyscallSuccessReg = ReturnValueReg;
-typedef union {
- IntReg intreg;
- FloatReg fpreg;
- CCReg ccreg;
- MiscReg ctrlreg;
-} AnyReg;
-
} // namespace ArmISA
#endif
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index b44283d..55c2dee 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -299,12 +299,6 @@
// This has to be one to prevent warnings that are treated as errors
constexpr unsigned NumVecRegs = 1;
-typedef union {
- IntReg intreg;
- FloatReg fpreg;
- MiscReg ctrlreg;
-} AnyReg;
-
} // namespace MipsISA
#endif
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 4e8c9e9..adbaae5 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -95,12 +95,6 @@
const int SyscallPseudoReturnReg = 3;
const int SyscallSuccessReg = 3;
-typedef union {
- IntReg intreg;
- FloatReg fpreg;
- MiscReg ctrlreg;
-} AnyReg;
-
enum MiscIntRegNums {
INTREG_CR = NumIntArchRegs,
INTREG_XER,
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 596fdf4..a7f4d2a 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -62,13 +62,6 @@
// This has to be one to prevent warnings that are treated as errors
constexpr unsigned NumVecRegs = 1;
-typedef union
-{
- IntReg intReg;
- FloatReg fpreg;
- MiscReg ctrlreg;
-} AnyReg;
-
// semantically meaningful register indices
const int ZeroReg = 0; // architecturally meaningful
// the rest of these depend on the ABI
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 9db3349..c2977f8 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -107,13 +107,6 @@
//technically for x87 (80 bits) or at all for xmm (128 bits)
typedef double FloatReg;
typedef uint64_t FloatRegBits;
-typedef union
-{
- IntReg intReg;
- FloatReg fpReg;
- CCReg ccReg;
- MiscReg ctrlReg;
-} AnyReg;
} // namespace X86ISA
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I659a0c5abc7883d82fedd1cac2cd103612d315c8
Gerrit-Change-Number: 13539
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: merged
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