Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13597
to review the following change.
Change subject: config: Create ArmRubySystem by refactoring SimpleSystem
......................................................................
config: Create ArmRubySystem by refactoring SimpleSystem
This patch is taking out non-memory related functionalities from
SimpleSystem in configs/arm/devices.py so that it can be inherited
by a new ArmRubySystem class. In this way we can instantiate
ArmSimpleSystem for systems using the legacy memory subsystem
and ArmRubySystem for systems using ruby.
Change-Id: Ida85924052f2de07e7e1a024f32482363f976d1a
Signed-off-by: Giacomo Travaglini <[email protected]>
Signed-off-by: Nikos Nikoleris <[email protected]>
---
M configs/example/arm/devices.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/starter_fs.py
3 files changed, 71 insertions(+), 38 deletions(-)
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 15492cb..6b98850 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017 ARM Limited
+# Copyright (c) 2016-2018 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -163,6 +163,13 @@
for cpu in self.cpus:
cpu.connectAllPorts(bus)
+ def connectRubySide(self, system):
+ for idx, cpu in enumerate(self.cpus):
+ cpu.icache_port = system.ruby._cpu_ports[idx].slave
+ cpu.dcache_port = system.ruby._cpu_ports[idx].slave
+ cpu.itb.walker.port = system.ruby._cpu_ports[idx].slave
+ cpu.dtb.walker.port = system.ruby._cpu_ports[idx].slave
+
class AtomicCluster(CpuCluster):
def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
@@ -180,12 +187,11 @@
def addL1(self):
pass
-
-class SimpleSystem(LinuxArmSystem):
+class ArmBaseSystem(LinuxArmSystem):
cache_line_size = 64
- def __init__(self, caches, mem_size, **kwargs):
- super(SimpleSystem, self).__init__(**kwargs)
+ def __init__(self, mem_size, **kwargs):
+ super(ArmBaseSystem, self).__init__(**kwargs)
self.voltage_domain = VoltageDomain(voltage="1.0V")
self.clk_domain = SrcClockDomain(clock="1GHz",
@@ -196,20 +202,41 @@
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
- self.membus = MemBus()
-
self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()
self.iobus = IOXBar()
- # CPUs->PIO
- self.iobridge = Bridge(delay='50ns')
# Device DMA -> MEM
mem_range = self.realview._mem_regions[0]
mem_range_size = long(mem_range[1]) - long(mem_range[0])
assert mem_range_size >= long(Addr(mem_size))
self.mem_ranges = [ AddrRange(start=mem_range[0], size=mem_size) ]
+
+ self._pci_devices = 0
+ self._clusters = []
+ self._num_cpus = 0
+
+ def numCpuClusters(self):
+ return len(self._clusters)
+
+ def addCpuCluster(self, cpu_cluster, num_cpus):
+ assert cpu_cluster not in self._clusters
+ assert num_cpus > 0
+ self._clusters.append(cpu_cluster)
+ self._num_cpus += num_cpus
+
+ def numCpus(self):
+ return self._num_cpus
+
+class ArmSimpleSystem(ArmBaseSystem):
+ def __init__(self, caches, mem_size, **kwargs):
+ super(ArmSimpleSystem, self).__init__(mem_size, **kwargs)
+
+ self.membus = MemBus()
+ # CPUs->PIO
+ self.iobridge = Bridge(delay='50ns')
+
self._caches = caches
if self._caches:
self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
@@ -217,15 +244,6 @@
self.dmabridge = Bridge(delay='50ns',
ranges=[self.mem_ranges[0]])
- self._pci_devices = 0
- self._clusters = []
- self._num_cpus = 0
-
- def attach_pci(self, dev):
- dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices +
1, 0)
- self._pci_devices += 1
- self.realview.attachPciDevice(dev, self.iobus)
-
def connect(self):
self.iobridge.master = self.iobus.slave
self.iobridge.slave = self.membus.master
@@ -242,17 +260,10 @@
self.realview.attachIO(self.iobus)
self.system_port = self.membus.slave
- def numCpuClusters(self):
- return len(self._clusters)
-
- def addCpuCluster(self, cpu_cluster, num_cpus):
- assert cpu_cluster not in self._clusters
- assert num_cpus > 0
- self._clusters.append(cpu_cluster)
- self._num_cpus += num_cpus
-
- def numCpus(self):
- return self._num_cpus
+ def attach_pci(self, dev):
+ dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices +
1, 0)
+ self._pci_devices += 1
+ self.realview.attachPciDevice(dev, self.iobus)
def addCaches(self, need_caches, last_cache_level):
if not need_caches:
@@ -280,3 +291,25 @@
# connect each cluster to the memory hierarchy
for cluster in self._clusters:
cluster.connectMemSide(cluster_mem_bus)
+
+class ArmRubySystem(ArmBaseSystem):
+ def __init__(self, mem_size, **kwargs):
+ super(ArmRubySystem, self).__init__(mem_size, **kwargs)
+
+ self._dma_ports = [ ]
+ self.highest_el_is_64 = True
+ self.machine_type = 'DTOnly'
+
+ def connect(self):
+ self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports)
+ self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
+
+ def attach_pci(self, dev):
+ dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices +
1, 0)
+ self._pci_devices += 1
+ self.realview.attachPciDevice(dev, self.iobus,
+ dma_ports=self._dma_ports)
+
+ def connectRubySide(self):
+ for cluster in self._clusters:
+ cluster.connectRubySide(self)
diff --git a/configs/example/arm/fs_bigLITTLE.py
b/configs/example/arm/fs_bigLITTLE.py
index 7d66c03..6c6de27 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -114,9 +114,9 @@
cpu_voltage, *cpu_config)
def createSystem(caches, kernel, bootscript, disks=[]):
- sys = devices.SimpleSystem(caches, default_mem_size,
- kernel=SysPaths.binary(kernel),
- readfile=bootscript)
+ sys = devices.ArmSimpleSystem(caches, default_mem_size,
+ kernel=SysPaths.binary(kernel),
+ readfile=bootscript)
sys.mem_ctrls = [ SimpleMemory(range=r, port=sys.membus.master)
for r in sys.mem_ranges ]
diff --git a/configs/example/arm/starter_fs.py
b/configs/example/arm/starter_fs.py
index a199768..3b1e121 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -107,12 +107,12 @@
# Only simulate caches when using a timing CPU (e.g., the HPI model)
want_caches = True if mem_mode == "timing" else False
- system = devices.SimpleSystem(want_caches,
- args.mem_size,
- mem_mode=mem_mode,
- dtb_filename=dtb_file,
- kernel=SysPaths.binary(args.kernel),
- readfile=args.script)
+ system = devices.ArmSimpleSystem(want_caches,
+ args.mem_size,
+ mem_mode=mem_mode,
+ dtb_filename=dtb_file,
+ kernel=SysPaths.binary(args.kernel),
+ readfile=args.script)
MemConfig.config_mem(args, system)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13597
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ida85924052f2de07e7e1a024f32482363f976d1a
Gerrit-Change-Number: 13597
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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