Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/13626
Change subject: arch: cpu: Stop passing around misc registers by reference.
......................................................................
arch: cpu: Stop passing around misc registers by reference.
These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.
Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
---
M src/arch/alpha/isa.cc
M src/arch/alpha/isa.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/power/isa.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/ua2005.cc
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
23 files changed, 58 insertions(+), 68 deletions(-)
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 32d1aff..685ddd4 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -114,7 +114,7 @@
}
void
-ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
+ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -140,8 +140,7 @@
}
void
-ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
- ThreadID tid)
+ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 36e7084..54e1202 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -77,10 +77,9 @@
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid
= 0);
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
- ThreadID tid = 0);
- void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext
*tc,
- ThreadID tid = 0);
+ void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0);
+ void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc,
+ ThreadID tid=0);
void
clear()
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 97ad0e2..ef6be07 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -696,7 +696,7 @@
}
void
-ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val)
+ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
{
assert(misc_reg < NumMiscRegs);
@@ -718,7 +718,7 @@
}
void
-ISA::setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
{
RegVal newVal = val;
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 57bc732..602c970 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -419,8 +419,8 @@
public:
RegVal readMiscRegNoEffect(int misc_reg) const;
RegVal readMiscReg(int misc_reg, ThreadContext *tc);
- void setMiscRegNoEffect(int misc_reg, const RegVal &val);
- void setMiscReg(int misc_reg, const RegVal &val, ThreadContext
*tc);
+ void setMiscRegNoEffect(int misc_reg, RegVal val);
+ void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
RegId
flattenRegId(const RegId& regId) const
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index df70bac..6f109f7 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -445,7 +445,7 @@
}
void
-ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
+ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
@@ -458,7 +458,7 @@
}
void
-ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
+ISA::setRegMask(int misc_reg, MiscReg val, ThreadID tid)
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
@@ -473,8 +473,7 @@
// be overwritten. Make sure to handle those particular registers
// with care!
void
-ISA::setMiscReg(int misc_reg, const MiscReg &val,
- ThreadContext *tc, ThreadID tid)
+ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
{
int reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
@@ -497,7 +496,7 @@
* (setRegWithEffect)
*/
MiscReg
-ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
+ISA::filterCP0Write(int misc_reg, int reg_sel, MiscReg val)
{
MiscReg retVal = val;
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 885ca2f..ffcb3f1 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -94,14 +94,13 @@
MiscReg readMiscReg(int misc_reg,
ThreadContext *tc, ThreadID tid = 0);
- MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg
&val);
- void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid =
0);
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
- ThreadID tid = 0);
+ MiscReg filterCP0Write(int misc_reg, int reg_sel, MiscReg val);
+ void setRegMask(int misc_reg, MiscReg val, ThreadID tid = 0);
+ void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0);
//template <class TC>
- void setMiscReg(int misc_reg, const MiscReg &val,
- ThreadContext *tc, ThreadID tid = 0);
+ void setMiscReg(int misc_reg, MiscReg val,
+ ThreadContext *tc, ThreadID tid=0);
//////////////////////////////////////////////////////////
//
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 9769f8f..4e9fdb0 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -76,13 +76,13 @@
}
void
- setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ setMiscRegNoEffect(int misc_reg, MiscReg val)
{
fatal("Power does not currently have any misc regs defined\n");
}
void
- setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+ setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc)
{
fatal("Power does not currently have any misc regs defined\n");
}
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 6824e70..40b18e8 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -158,7 +158,7 @@
}
void
-ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ISA::setMiscRegNoEffect(int misc_reg, MiscReg val)
{
if (misc_reg > NumMiscRegs || misc_reg < 0) {
// Illegal CSR
@@ -169,7 +169,7 @@
}
void
-ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc)
{
if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
// Ignore writes to HPM counters for now
@@ -185,4 +185,4 @@
RiscvISAParams::create()
{
return new RiscvISA::ISA(this);
-}
\ No newline at end of file
+}
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index f96b072..2602f6d 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -76,8 +76,8 @@
MiscReg readMiscRegNoEffect(int misc_reg) const;
MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
- void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
+ void setMiscRegNoEffect(int misc_reg, MiscReg val);
+ void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc);
RegId flattenRegId(const RegId ®Id) const { return regId; }
int flattenIntIndex(int reg) const { return reg; }
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 82fee0d..9209ba3 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -116,7 +116,7 @@
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
- void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
+ void setFSReg(int miscReg, MiscReg val, ThreadContext *tc);
MiscReg readFSReg(int miscReg, ThreadContext * tc);
// Update interrupt state on softint or pil change
@@ -186,9 +186,8 @@
MiscReg readMiscRegNoEffect(int miscReg) const;
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
- void setMiscRegNoEffect(int miscReg, const MiscReg val);
- void setMiscReg(int miscReg, const MiscReg val,
- ThreadContext *tc);
+ void setMiscRegNoEffect(int miscReg, MiscReg val);
+ void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
RegId
flattenRegId(const RegId& regId) const
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index d8af29b..1a248d3 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -88,7 +88,7 @@
}
void
-ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
+ISA::setFSReg(int miscReg, MiscReg val, ThreadContext *tc)
{
BaseCPU *cpu = tc->getCpuPtr();
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 21bd4fd..abd099b 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -433,7 +433,7 @@
}
void
- setMiscRegNoEffect(int misc_reg, const RegVal &val)
+ setMiscRegNoEffect(int misc_reg, RegVal val)
{
DPRINTF(Checker, "Setting misc reg %d with no effect to check
later\n",
misc_reg);
@@ -442,7 +442,7 @@
}
void
- setMiscReg(int misc_reg, const RegVal &val) override
+ setMiscReg(int misc_reg, RegVal val) override
{
DPRINTF(Checker, "Setting misc reg %d with effect to check
later\n",
misc_reg);
@@ -459,8 +459,7 @@
}
void
- setMiscRegOperand(const StaticInst *si, int idx,
- const RegVal &val) override
+ setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index 90e6526..242b3c1 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -361,7 +361,7 @@
{ return actualTC->readMiscReg(misc_reg); }
void
- setMiscRegNoEffect(int misc_reg, const RegVal &val)
+ setMiscRegNoEffect(int misc_reg, RegVal val)
{
DPRINTF(Checker, "Setting misc reg with no effect: %d to both
Checker"
" and O3..\n", misc_reg);
@@ -370,7 +370,7 @@
}
void
- setMiscReg(int misc_reg, const RegVal &val)
+ setMiscReg(int misc_reg, RegVal val)
{
DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
" and O3..\n", misc_reg);
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index df1c020..1709014 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -189,7 +189,7 @@
*/
virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
virtual void setMiscRegOperand(const StaticInst *si,
- int idx, const RegVal &val) = 0;
+ int idx, RegVal val) = 0;
/**
* Reads a miscellaneous register, handling any architectural
@@ -201,7 +201,7 @@
* Sets a miscellaneous register, handling any architectural
* side effects due to writing that register.
*/
- virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;
+ virtual void setMiscReg(int misc_reg, RegVal val) = 0;
/** @} */
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 44b0bd7..e416d6a 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -325,7 +325,7 @@
}
void
- setMiscReg(int misc_reg, const RegVal &val) override
+ setMiscReg(int misc_reg, RegVal val) override
{
thread.setMiscReg(misc_reg, val);
}
@@ -339,8 +339,7 @@
}
void
- setMiscRegOperand(const StaticInst *si, int idx,
- const RegVal &val) override
+ setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
@@ -447,7 +446,7 @@
}
void
- setRegOtherThread(const RegId ®, const RegVal &val,
+ setRegOtherThread(const RegId ®, RegVal val,
ThreadID tid=InvalidThreadID)
{
SimpleThread *other_thread = (tid == InvalidThreadID
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 1668b3a..8b2af0c 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1260,16 +1260,14 @@
template <class Impl>
void
-FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
- const RegVal &val, ThreadID tid)
+FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
{
this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
}
template <class Impl>
void
-FullO3CPU<Impl>::setMiscReg(int misc_reg,
- const RegVal &val, ThreadID tid)
+FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
{
miscRegfileWrites++;
this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index a52e5ed..fa9e0c6 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -390,12 +390,12 @@
RegVal readMiscReg(int misc_reg, ThreadID tid);
/** Sets a miscellaneous register. */
- void setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid);
+ void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
- void setMiscReg(int misc_reg, const RegVal &val, ThreadID tid);
+ void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
RegVal readIntReg(PhysRegIdPtr phys_reg);
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 6e95d2f..2233163 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -146,7 +146,7 @@
* might have as defined by the architecture.
*/
void
- setMiscReg(int misc_reg, const RegVal &val)
+ setMiscReg(int misc_reg, RegVal val)
{
/** Writes to misc. registers are recorded and deferred until the
* commit stage, when updateMiscRegs() is called. First, check if
@@ -182,7 +182,7 @@
* might have as defined by the architecture.
*/
void
- setMiscRegOperand(const StaticInst *si, int idx, const RegVal &val)
+ setMiscRegOperand(const StaticInst *si, int idx, RegVal val)
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index c55ea5d..cdbdf0a 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -344,11 +344,11 @@
{ return cpu->readMiscReg(misc_reg, thread->threadId()); }
/** Sets a misc. register. */
- virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val);
+ virtual void setMiscRegNoEffect(int misc_reg, RegVal val);
/** Sets a misc. register, including any side-effects the
* write might have as defined by the architecture. */
- virtual void setMiscReg(int misc_reg, const RegVal &val);
+ virtual void setMiscReg(int misc_reg, RegVal val);
virtual RegId flattenRegId(const RegId& regId) const;
diff --git a/src/cpu/o3/thread_context_impl.hh
b/src/cpu/o3/thread_context_impl.hh
index 9852cb0..245c8e0 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -323,7 +323,7 @@
template <class Impl>
void
-O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val)
+O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val)
{
cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
@@ -333,7 +333,7 @@
#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
template <class Impl>
void
-O3ThreadContext<Impl>::setMiscReg(int misc_reg, const RegVal &val)
+O3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val)
{
cpu->setMiscReg(misc_reg, val, thread->threadId());
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index af6485f..daaac8e 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -381,8 +381,7 @@
}
void
- setMiscRegOperand(const StaticInst *si, int idx,
- const RegVal &val) override
+ setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
numIntRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -406,7 +405,7 @@
* side effects due to writing that register.
*/
void
- setMiscReg(int misc_reg, const RegVal &val) override
+ setMiscReg(int misc_reg, RegVal val) override
{
numIntRegWrites++;
thread->setMiscReg(misc_reg, val);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 41e6794..29c52a5 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -513,13 +513,13 @@
}
void
- setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid = 0)
+ setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0)
{
return isa->setMiscRegNoEffect(misc_reg, val);
}
void
- setMiscReg(int misc_reg, const RegVal &val, ThreadID tid = 0)
+ setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0)
{
return isa->setMiscReg(misc_reg, val, tc);
}
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index e3a576b..57a0024 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -282,9 +282,9 @@
virtual RegVal readMiscReg(int misc_reg) = 0;
- virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val) = 0;
+ virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0;
- virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;
+ virtual void setMiscReg(int misc_reg, RegVal val) = 0;
virtual RegId flattenRegId(const RegId& regId) const = 0;
@@ -295,7 +295,7 @@
}
virtual void
- setRegOtherThread(const RegId& misc_reg, const RegVal &val, ThreadID
tid)
+ setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
{
}
@@ -554,10 +554,10 @@
RegVal readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }
- void setMiscRegNoEffect(int misc_reg, const RegVal &val)
+ void setMiscRegNoEffect(int misc_reg, RegVal val)
{ return actualTC->setMiscRegNoEffect(misc_reg, val); }
- void setMiscReg(int misc_reg, const RegVal &val)
+ void setMiscReg(int misc_reg, RegVal val)
{ return actualTC->setMiscReg(misc_reg, val); }
RegId flattenRegId(const RegId& regId) const
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Gerrit-Change-Number: 13626
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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