Giacomo Travaglini has uploaded a new patch set (#4) to the change
originally created by Giacomo Gabrielli. (
https://gem5-review.googlesource.com/c/public/gem5/+/13518 )
Change subject: mem: Add support for partial stores and wide memory accesses
......................................................................
mem: Add support for partial stores and wide memory accesses
This changeset adds support for partial (or masked) stores, i.e.
stores that can disable writes to individual bytes within the target
address range. In addition, this changeset extends the code to crack
memory accesses across most CPU models (TimingSimpleCPU still TBD), so
that arbitrarily wide memory accesses are supported. These changes
are required for supporting ISAs with wide vectors.
Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92
Signed-off-by: Giacomo Gabrielli <[email protected]>
---
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
A src/cpu/utils.hh
M src/mem/abstract_mem.cc
M src/mem/cache/cache.cc
M src/mem/packet.hh
M src/mem/request.hh
21 files changed, 409 insertions(+), 170 deletions(-)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92
Gerrit-Change-Number: 13518
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-CC: Daniel Carvalho <[email protected]>
Gerrit-MessageType: newpatchset
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