Giacomo Travaglini has uploaded a new patch set (#4) to the change
originally created by Giacomo Gabrielli. (
https://gem5-review.googlesource.com/c/public/gem5/+/13517 )
Change subject: cpu-o3: Add cache read ports limit to LSQ
......................................................................
cpu-o3: Add cache read ports limit to LSQ
This change introduces cache read ports to limit the number of
per-cycle loads. Previously only the number of per-cycle stores
could be limited.
Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4
Signed-off-by: Gabor Dozsa <[email protected]>
Reviewed-by: Giacomo Gabrielli <[email protected]>
---
M src/cpu/o3/O3CPU.py
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit_impl.hh
4 files changed, 50 insertions(+), 19 deletions(-)
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4
Gerrit-Change-Number: 13517
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Gabor Dozsa <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-CC: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: newpatchset
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