Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13779 )
Change subject: arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
......................................................................
arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
While there is a AArch32 class for instructions accessing implementation
defined registers, we are lacking for the AArch64 counterpart.
we were relying on FailUnimplemented, which is untrappable at EL2 (except
for HCR_EL2.TGE) since it is just raising Undefined Instruction.
Change-Id: I923cb914658ca958af031612cf005159707b0b4f
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13779
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/formats/aarch64.isa
3 files changed, 67 insertions(+), 7 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index b2761e7..7df2f76 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -266,6 +266,8 @@
assert(miscRead);
trap_to_hyp = hcr.tid1 && el == EL1;
break;
+ case MISCREG_IMPDEF_UNIMPL:
+ trap_to_hyp = hcr.tidcp && el == EL1;
default:
break;
}
@@ -330,3 +332,33 @@
printMiscReg(ss, op1);
return ss.str();
}
+
+Fault
+MiscRegImplDefined64::execute(ExecContext *xc,
+ Trace::InstRecord *traceData) const
+{
+ auto tc = xc->tcBase();
+ const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+ const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
+
+ Fault fault = trap(tc, miscReg, el, imm);
+
+ if (fault != NoFault) {
+ return fault;
+
+ } else if (warning) {
+ warn_once("\tinstruction '%s' unimplemented\n",
fullMnemonic.c_str());
+ return NoFault;
+
+ } else {
+ return std::make_shared<UndefinedInstruction>(machInst, false,
+ mnemonic);
+ }
+}
+
+std::string
+MiscRegImplDefined64::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+{
+ return csprintf("%-10s (implementation defined)",
fullMnemonic.c_str());
+}
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 8af488a..f70344b 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -178,4 +178,32 @@
Addr pc, const SymbolTable *symtab) const override;
};
+class MiscRegImplDefined64 : public MiscRegOp64
+{
+ protected:
+ const std::string fullMnemonic;
+ const MiscRegIndex miscReg;
+ const uint32_t imm;
+ const bool warning;
+
+ public:
+ MiscRegImplDefined64(const char *mnem, ExtMachInst _machInst,
+ MiscRegIndex misc_reg, bool misc_read,
+ uint32_t _imm, const std::string full_mnem,
+ bool _warning) :
+ MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
+ fullMnemonic(full_mnem), miscReg(misc_reg), imm(_imm),
+ warning(_warning)
+ {
+ assert(miscReg == MISCREG_IMPDEF_UNIMPL);
+ }
+
+ protected:
+ Fault execute(ExecContext *xc,
+ Trace::InstRecord *traceData) const override;
+
+ std::string generateDisassembly(
+ Addr pc, const SymbolTable *symtab) const override;
+};
+
#endif
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index 26c65ec..3f4e337 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -446,13 +446,13 @@
read ? "mrs" : "msr",
op0, op1, crn, crm, op2);
- if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
- return new
WarnUnimplemented(read ? "mrs" : "msr",
- machInst, full_mnemonic + " treated as
NOP");
- } else {
- return new
FailUnimplemented(read ? "mrs" : "msr",
- machInst, full_mnemonic);
- }
+ uint32_t iss = msrMrs64IssBuild(
+ read, op0, op1, crn, crm, op2, rt);
+
+ return new MiscRegImplDefined64(
+ read ? "mrs" : "msr",
+ machInst, miscReg, read, iss, full_mnemonic,
+ miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]);
} else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
if (miscReg == MISCREG_NZCV) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I923cb914658ca958af031612cf005159707b0b4f
Gerrit-Change-Number: 13779
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: merged
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