Jairo Balart has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/14235
Change subject: arch-arm: Add GICv3 MiscRegs
......................................................................
arch-arm: Add GICv3 MiscRegs
Change-Id: I0059bd13c9a416803b0d0f2d158c11d856e2990c
---
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
2 files changed, 1,258 insertions(+), 10 deletions(-)
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 07123bd..e4369c1 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -287,6 +287,11 @@
return MISCREG_DACR;
}
break;
+ case 4:
+ if (opc1 == 0 && crm == 6 && opc2 == 0) {
+ return MISCREG_ICC_PMR;
+ }
+ break;
case 5:
if (opc1 == 0) {
if (crm == 0) {
@@ -668,10 +673,193 @@
if (opc2 == 0) {
return MISCREG_ISR;
}
+ } else if (crm == 8) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_ICC_IAR0;
+ case 1:
+ return MISCREG_ICC_EOIR0;
+ case 2:
+ return MISCREG_ICC_HPPIR0;
+ case 3:
+ return MISCREG_ICC_BPR0;
+ case 4:
+ return MISCREG_ICC_AP0R0;
+ case 5:
+ return MISCREG_ICC_AP0R1;
+ case 6:
+ return MISCREG_ICC_AP0R2;
+ case 7:
+ return MISCREG_ICC_AP0R3;
+ }
+ } else if (crm == 9) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_ICC_AP1R0;
+ case 1:
+ return MISCREG_ICC_AP1R1;
+ case 2:
+ return MISCREG_ICC_AP1R2;
+ case 3:
+ return MISCREG_ICC_AP1R3;
+ }
+ } else if (crm == 11) {
+ switch (opc2) {
+ case 1:
+ return MISCREG_ICC_DIR;
+ case 3:
+ return MISCREG_ICC_RPR;
+ }
+ } else if (crm == 12) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_ICC_IAR1;
+ case 1:
+ return MISCREG_ICC_EOIR1;
+ case 2:
+ return MISCREG_ICC_HPPIR1;
+ case 3:
+ return MISCREG_ICC_BPR1;
+ case 4:
+ return MISCREG_ICC_CTLR;
+ case 5:
+ return MISCREG_ICC_SRE;
+ case 6:
+ return MISCREG_ICC_IGRPEN0;
+ case 7:
+ return MISCREG_ICC_IGRPEN1;
+ }
}
} else if (opc1 == 4) {
- if (crm == 0 && opc2 == 0)
+ if (crm == 0 && opc2 == 0) {
return MISCREG_HVBAR;
+ } else if (crm == 8) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_ICH_AP0R0;
+ case 1:
+ return MISCREG_ICH_AP0R1;
+ case 2:
+ return MISCREG_ICH_AP0R2;
+ case 3:
+ return MISCREG_ICH_AP0R3;
+ }
+ } else if (crm == 9) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_ICH_AP1R0;
+ case 1:
+ return MISCREG_ICH_AP1R1;
+ case 2:
+ return MISCREG_ICH_AP1R2;
+ case 3:
+ return MISCREG_ICH_AP1R3;
+ case 5:
+ return MISCREG_ICC_HSRE;
+ }
+ } else if (crm == 11) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_ICH_HCR;
+ case 1:
+ return MISCREG_ICH_VTR;
+ case 2:
+ return MISCREG_ICH_MISR;
+ case 3:
+ return MISCREG_ICH_EISR;
+ case 5:
+ return MISCREG_ICH_ELRSR;
+ case 7:
+ return MISCREG_ICH_VMCR;
+ }
+ } else if (crm == 12) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_ICH_LR0;
+ case 1:
+ return MISCREG_ICH_LR1;
+ case 2:
+ return MISCREG_ICH_LR2;
+ case 3:
+ return MISCREG_ICH_LR3;
+ case 4:
+ return MISCREG_ICH_LR4;
+ case 5:
+ return MISCREG_ICH_LR5;
+ case 6:
+ return MISCREG_ICH_LR6;
+ case 7:
+ return MISCREG_ICH_LR7;
+ }
+ } else if (crm == 13) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_ICH_LR8;
+ case 1:
+ return MISCREG_ICH_LR9;
+ case 2:
+ return MISCREG_ICH_LR10;
+ case 3:
+ return MISCREG_ICH_LR11;
+ case 4:
+ return MISCREG_ICH_LR12;
+ case 5:
+ return MISCREG_ICH_LR13;
+ case 6:
+ return MISCREG_ICH_LR14;
+ case 7:
+ return MISCREG_ICH_LR15;
+ }
+ } else if (crm == 14) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_ICH_LRC0;
+ case 1:
+ return MISCREG_ICH_LRC1;
+ case 2:
+ return MISCREG_ICH_LRC2;
+ case 3:
+ return MISCREG_ICH_LRC3;
+ case 4:
+ return MISCREG_ICH_LRC4;
+ case 5:
+ return MISCREG_ICH_LRC5;
+ case 6:
+ return MISCREG_ICH_LRC6;
+ case 7:
+ return MISCREG_ICH_LRC7;
+ }
+ } else if (crm == 15) {
+ switch (opc2) {
+ case 0:
+ return MISCREG_ICH_LRC8;
+ case 1:
+ return MISCREG_ICH_LRC9;
+ case 2:
+ return MISCREG_ICH_LRC10;
+ case 3:
+ return MISCREG_ICH_LRC11;
+ case 4:
+ return MISCREG_ICH_LRC12;
+ case 5:
+ return MISCREG_ICH_LRC13;
+ case 6:
+ return MISCREG_ICH_LRC14;
+ case 7:
+ return MISCREG_ICH_LRC15;
+ }
+ }
+ } else if (opc1 == 6) {
+ if (crm == 12) {
+ switch (opc2) {
+ case 4:
+ return MISCREG_ICC_MCTLR;
+ case 5:
+ return MISCREG_ICC_MSRE;
+ case 7:
+ return MISCREG_ICC_MGRPEN1;
+ }
+ }
}
break;
case 13:
@@ -1761,6 +1949,12 @@
return MISCREG_CURRENTEL;
}
break;
+ case 6:
+ switch (op2) {
+ case 0:
+ return MISCREG_ICC_PMR_EL1;
+ }
+ break;
}
break;
case 3:
@@ -2140,6 +2334,72 @@
return MISCREG_DISR_EL1;
}
break;
+ case 8:
+ switch (op2) {
+ case 0:
+ return MISCREG_ICC_IAR0_EL1;
+ case 1:
+ return MISCREG_ICC_EOIR0_EL1;
+ case 2:
+ return MISCREG_ICC_HPPIR0_EL1;
+ case 3:
+ return MISCREG_ICC_BPR0_EL1;
+ case 4:
+ return MISCREG_ICC_AP0R0_EL1;
+ case 5:
+ return MISCREG_ICC_AP0R1_EL1;
+ case 6:
+ return MISCREG_ICC_AP0R2_EL1;
+ case 7:
+ return MISCREG_ICC_AP0R3_EL1;
+ }
+ break;
+ case 9:
+ switch (op2) {
+ case 0:
+ return MISCREG_ICC_AP1R0_EL1;
+ case 1:
+ return MISCREG_ICC_AP1R1_EL1;
+ case 2:
+ return MISCREG_ICC_AP1R2_EL1;
+ case 3:
+ return MISCREG_ICC_AP1R3_EL1;
+ }
+ break;
+ case 11:
+ switch (op2) {
+ case 1:
+ return MISCREG_ICC_DIR_EL1;
+ case 3:
+ return MISCREG_ICC_RPR_EL1;
+ case 5:
+ return MISCREG_ICC_SGI1R_EL1;
+ case 6:
+ return MISCREG_ICC_ASGI1R_EL1;
+ case 7:
+ return MISCREG_ICC_SGI0R_EL1;
+ }
+ break;
+ case 12:
+ switch (op2) {
+ case 0:
+ return MISCREG_ICC_IAR1_EL1;
+ case 1:
+ return MISCREG_ICC_EOIR1_EL1;
+ case 2:
+ return MISCREG_ICC_HPPIR1_EL1;
+ case 3:
+ return MISCREG_ICC_BPR1_EL1;
+ case 4:
+ return MISCREG_ICC_CTLR_EL1;
+ case 5:
+ return MISCREG_ICC_SRE_EL1;
+ case 6:
+ return MISCREG_ICC_IGRPEN0_EL1;
+ case 7:
+ return MISCREG_ICC_IGRPEN1_EL1;
+ }
+ break;
}
break;
case 4:
@@ -2158,6 +2418,88 @@
return MISCREG_VDISR_EL2;
}
break;
+ case 8:
+ switch (op2) {
+ case 0:
+ return MISCREG_ICH_AP0R0_EL2;
+ case 1:
+ return MISCREG_ICH_AP0R1_EL2;
+ case 2:
+ return MISCREG_ICH_AP0R2_EL2;
+ case 3:
+ return MISCREG_ICH_AP0R3_EL2;
+ }
+ break;
+ case 9:
+ switch (op2) {
+ case 0:
+ return MISCREG_ICH_AP1R0_EL2;
+ case 1:
+ return MISCREG_ICH_AP1R1_EL2;
+ case 2:
+ return MISCREG_ICH_AP1R2_EL2;
+ case 3:
+ return MISCREG_ICH_AP1R3_EL2;
+ case 5:
+ return MISCREG_ICC_SRE_EL2;
+ }
+ break;
+ case 11:
+ switch (op2) {
+ case 0:
+ return MISCREG_ICH_HCR_EL2;
+ case 1:
+ return MISCREG_ICH_VTR_EL2;
+ case 2:
+ return MISCREG_ICH_MISR_EL2;
+ case 3:
+ return MISCREG_ICH_EISR_EL2;
+ case 5:
+ return MISCREG_ICH_ELRSR_EL2;
+ case 7:
+ return MISCREG_ICH_VMCR_EL2;
+ }
+ break;
+ case 12:
+ switch (op2) {
+ case 0:
+ return MISCREG_ICH_LR0_EL2;
+ case 1:
+ return MISCREG_ICH_LR1_EL2;
+ case 2:
+ return MISCREG_ICH_LR2_EL2;
+ case 3:
+ return MISCREG_ICH_LR3_EL2;
+ case 4:
+ return MISCREG_ICH_LR4_EL2;
+ case 5:
+ return MISCREG_ICH_LR5_EL2;
+ case 6:
+ return MISCREG_ICH_LR6_EL2;
+ case 7:
+ return MISCREG_ICH_LR7_EL2;
+ }
+ break;
+ case 13:
+ switch (op2) {
+ case 0:
+ return MISCREG_ICH_LR8_EL2;
+ case 1:
+ return MISCREG_ICH_LR9_EL2;
+ case 2:
+ return MISCREG_ICH_LR10_EL2;
+ case 3:
+ return MISCREG_ICH_LR11_EL2;
+ case 4:
+ return MISCREG_ICH_LR12_EL2;
+ case 5:
+ return MISCREG_ICH_LR13_EL2;
+ case 6:
+ return MISCREG_ICH_LR14_EL2;
+ case 7:
+ return MISCREG_ICH_LR15_EL2;
+ }
+ break;
}
break;
case 6:
@@ -2172,6 +2514,16 @@
return MISCREG_RMR_EL3;
}
break;
+ case 12:
+ switch (op2) {
+ case 4:
+ return MISCREG_ICC_CTLR_EL3;
+ case 5:
+ return MISCREG_ICC_SRE_EL3;
+ case 7:
+ return MISCREG_ICC_IGRPEN1_EL3;
+ }
+ break;
}
break;
}
@@ -4032,6 +4384,470 @@
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CONTEXTIDR_EL2)
.mon().hyp();
+
+ // GICv3 AArch64
+ InitReg(MISCREG_ICC_PMR_EL1)
+ .res0(0xffffff00) // [31:8]
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_PMR);
+ InitReg(MISCREG_ICC_IAR0_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_IAR0);
+ InitReg(MISCREG_ICC_EOIR0_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_EOIR0);
+ InitReg(MISCREG_ICC_HPPIR0_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_HPPIR0);
+ InitReg(MISCREG_ICC_BPR0_EL1)
+ .res0(0xfffffff8) // [31:3]
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_BPR0);
+ InitReg(MISCREG_ICC_AP0R0_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_AP0R0);
+ InitReg(MISCREG_ICC_AP0R1_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_AP0R1);
+ InitReg(MISCREG_ICC_AP0R2_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_AP0R2);
+ InitReg(MISCREG_ICC_AP0R3_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_AP0R3);
+ InitReg(MISCREG_ICC_AP1R0_EL1)
+ .banked()
+ .mapsTo(MISCREG_ICC_AP1R0);
+ InitReg(MISCREG_ICC_AP1R0_EL1_NS)
+ .bankedChild()
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_AP1R0_NS);
+ InitReg(MISCREG_ICC_AP1R0_EL1_S)
+ .bankedChild()
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_AP1R0_S);
+ InitReg(MISCREG_ICC_AP1R1_EL1)
+ .banked()
+ .mapsTo(MISCREG_ICC_AP1R1);
+ InitReg(MISCREG_ICC_AP1R1_EL1_NS)
+ .bankedChild()
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_AP1R1_NS);
+ InitReg(MISCREG_ICC_AP1R1_EL1_S)
+ .bankedChild()
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_AP1R1_S);
+ InitReg(MISCREG_ICC_AP1R2_EL1)
+ .banked()
+ .mapsTo(MISCREG_ICC_AP1R2);
+ InitReg(MISCREG_ICC_AP1R2_EL1_NS)
+ .bankedChild()
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_AP1R2_NS);
+ InitReg(MISCREG_ICC_AP1R2_EL1_S)
+ .bankedChild()
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_AP1R2_S);
+ InitReg(MISCREG_ICC_AP1R3_EL1)
+ .banked()
+ .mapsTo(MISCREG_ICC_AP1R3);
+ InitReg(MISCREG_ICC_AP1R3_EL1_NS)
+ .bankedChild()
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_AP1R3_NS);
+ InitReg(MISCREG_ICC_AP1R3_EL1_S)
+ .bankedChild()
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_AP1R3_S);
+ InitReg(MISCREG_ICC_DIR_EL1)
+ .res0(0xFF000000) // [31:24]
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_DIR);
+ InitReg(MISCREG_ICC_RPR_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_RPR);
+ InitReg(MISCREG_ICC_SGI1R_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_SGI1R);
+ InitReg(MISCREG_ICC_ASGI1R_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_ASGI1R);
+ InitReg(MISCREG_ICC_SGI0R_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_SGI0R);
+ InitReg(MISCREG_ICC_IAR1_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_IAR1);
+ InitReg(MISCREG_ICC_EOIR1_EL1)
+ .res0(0xFF000000) // [31:24]
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_EOIR1);
+ InitReg(MISCREG_ICC_HPPIR1_EL1)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_HPPIR1);
+ InitReg(MISCREG_ICC_BPR1_EL1)
+ .banked()
+ .mapsTo(MISCREG_ICC_BPR1);
+ InitReg(MISCREG_ICC_BPR1_EL1_NS)
+ .bankedChild()
+ .res0(0xfffffff8) // [31:3]
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_BPR1_NS);
+ InitReg(MISCREG_ICC_BPR1_EL1_S)
+ .bankedChild()
+ .res0(0xfffffff8) // [31:3]
+ .secure().exceptUserMode()
+ .mapsTo(MISCREG_ICC_BPR1_S);
+ InitReg(MISCREG_ICC_CTLR_EL1)
+ .banked()
+ .mapsTo(MISCREG_ICC_CTLR);
+ InitReg(MISCREG_ICC_CTLR_EL1_NS)
+ .bankedChild()
+ .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_CTLR_NS);
+ InitReg(MISCREG_ICC_CTLR_EL1_S)
+ .bankedChild()
+ .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
+ .secure().exceptUserMode()
+ .mapsTo(MISCREG_ICC_CTLR_S);
+ InitReg(MISCREG_ICC_SRE_EL1)
+ .banked()
+ .mapsTo(MISCREG_ICC_SRE);
+ InitReg(MISCREG_ICC_SRE_EL1_NS)
+ .bankedChild()
+ .res0(0xFFFFFFF8) // [31:3]
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_SRE_NS);
+ InitReg(MISCREG_ICC_SRE_EL1_S)
+ .bankedChild()
+ .res0(0xFFFFFFF8) // [31:3]
+ .secure().exceptUserMode()
+ .mapsTo(MISCREG_ICC_SRE_S);
+ InitReg(MISCREG_ICC_IGRPEN0_EL1)
+ .res0(0xFFFFFFFE) // [31:1]
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_IGRPEN0);
+ InitReg(MISCREG_ICC_IGRPEN1_EL1)
+ .banked()
+ .mapsTo(MISCREG_ICC_IGRPEN1);
+ InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
+ .bankedChild()
+ .res0(0xFFFFFFFE) // [31:1]
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_IGRPEN1_NS);
+ InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
+ .bankedChild()
+ .res0(0xFFFFFFFE) // [31:1]
+ .secure().exceptUserMode()
+ .mapsTo(MISCREG_ICC_IGRPEN1_S);
+ InitReg(MISCREG_ICC_SRE_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICC_HSRE);
+ InitReg(MISCREG_ICC_CTLR_EL3)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_MCTLR);
+ InitReg(MISCREG_ICC_SRE_EL3)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_MSRE);
+ InitReg(MISCREG_ICC_IGRPEN1_EL3)
+ .allPrivileges().exceptUserMode()
+ .mapsTo(MISCREG_ICC_MGRPEN1);
+
+ InitReg(MISCREG_ICH_AP0R0_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_AP0R0);
+ InitReg(MISCREG_ICH_AP0R1_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_AP0R1);
+ InitReg(MISCREG_ICH_AP0R2_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_AP0R2);
+ InitReg(MISCREG_ICH_AP0R3_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_AP0R3);
+ InitReg(MISCREG_ICH_AP1R0_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_AP1R0);
+ InitReg(MISCREG_ICH_AP1R1_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_AP1R1);
+ InitReg(MISCREG_ICH_AP1R2_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_AP1R2);
+ InitReg(MISCREG_ICH_AP1R3_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_AP1R3);
+ InitReg(MISCREG_ICH_HCR_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_HCR);
+ InitReg(MISCREG_ICH_VTR_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_VTR);
+ InitReg(MISCREG_ICH_MISR_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_MISR);
+ InitReg(MISCREG_ICH_EISR_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_EISR);
+ InitReg(MISCREG_ICH_ELRSR_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_ELRSR);
+ InitReg(MISCREG_ICH_VMCR_EL2)
+ .hyp().mon()
+ .mapsTo(MISCREG_ICH_VMCR);
+ InitReg(MISCREG_ICH_LR0_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR1_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR2_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR3_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR4_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR5_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR6_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR7_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR8_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR9_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR10_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR11_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR12_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR13_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR14_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICH_LR15_EL2)
+ .hyp().mon()
+ .allPrivileges().exceptUserMode();
+
+ // GICv3 AArch32
+ InitReg(MISCREG_ICC_AP0R0)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP0R1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP0R2)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP0R3)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP1R0)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP1R0_NS)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP1R0_S)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP1R1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP1R1_NS)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP1R1_S)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP1R2)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP1R2_NS)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP1R2_S)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP1R3)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP1R3_NS)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_AP1R3_S)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_ASGI1R)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_BPR0)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_BPR1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_BPR1_NS)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_BPR1_S)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_CTLR)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_CTLR_NS)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_CTLR_S)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_DIR)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_EOIR0)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_EOIR1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_HPPIR0)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_HPPIR1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_HSRE)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_IAR0)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_IAR1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_IGRPEN0)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_IGRPEN1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_IGRPEN1_NS)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_IGRPEN1_S)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_MCTLR)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_MGRPEN1)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_MSRE)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_PMR)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_RPR)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_SGI0R)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_SGI1R)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_SRE)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_SRE_NS)
+ .allPrivileges().exceptUserMode();
+ InitReg(MISCREG_ICC_SRE_S)
+ .allPrivileges().exceptUserMode();
+
+ InitReg(MISCREG_ICH_AP0R0)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_AP0R1)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_AP0R2)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_AP0R3)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_AP1R0)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_AP1R1)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_AP1R2)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_AP1R3)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_HCR)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_VTR)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_MISR)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_EISR)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_ELRSR)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_VMCR)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR0)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR1)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR2)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR3)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR4)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR5)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR6)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR7)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR8)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR9)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR10)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR11)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR12)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR13)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR14)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LR15)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC0)
+ .mapsTo(MISCREG_ICH_LR0)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC1)
+ .mapsTo(MISCREG_ICH_LR1)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC2)
+ .mapsTo(MISCREG_ICH_LR2)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC3)
+ .mapsTo(MISCREG_ICH_LR3)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC4)
+ .mapsTo(MISCREG_ICH_LR4)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC5)
+ .mapsTo(MISCREG_ICH_LR5)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC6)
+ .mapsTo(MISCREG_ICH_LR6)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC7)
+ .mapsTo(MISCREG_ICH_LR7)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC8)
+ .mapsTo(MISCREG_ICH_LR8)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC9)
+ .mapsTo(MISCREG_ICH_LR9)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC10)
+ .mapsTo(MISCREG_ICH_LR10)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC11)
+ .mapsTo(MISCREG_ICH_LR11)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC12)
+ .mapsTo(MISCREG_ICH_LR12)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC13)
+ .mapsTo(MISCREG_ICH_LR13)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC14)
+ .mapsTo(MISCREG_ICH_LR14)
+ .hyp().mon();
+ InitReg(MISCREG_ICH_LRC15)
+ .mapsTo(MISCREG_ICH_LR15)
+ .hyp().mon();
+
InitReg(MISCREG_CNTHV_CTL_EL2)
.mon().hyp();
InitReg(MISCREG_CNTHV_CVAL_EL2)
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index ab3fc8f..5a24a7e 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -668,21 +668,236 @@
// Introduced in ARMv8.1
MISCREG_TTBR1_EL2, // 600
- MISCREG_CNTHV_CTL_EL2, // 601
- MISCREG_CNTHV_CVAL_EL2, // 602
- MISCREG_CNTHV_TVAL_EL2, // 603
- MISCREG_ID_AA64MMFR2_EL1, // 604
- // These MISCREG_FREESLOT are available Misc Register
- // slots for future registers to be implemented.
- MISCREG_FREESLOT_1, // 605
+ // GICv3, CPU interface
+ MISCREG_ICC_PMR_EL1, // 601
+ MISCREG_ICC_IAR0_EL1, // 602
+ MISCREG_ICC_EOIR0_EL1, // 603
+ MISCREG_ICC_HPPIR0_EL1, // 604
+ MISCREG_ICC_BPR0_EL1, // 605
+ MISCREG_ICC_AP0R0_EL1, // 606
+ MISCREG_ICC_AP0R1_EL1, // 607
+ MISCREG_ICC_AP0R2_EL1, // 608
+ MISCREG_ICC_AP0R3_EL1, // 609
+ MISCREG_ICC_AP1R0_EL1, // 610
+ MISCREG_ICC_AP1R0_EL1_NS, // 611
+ MISCREG_ICC_AP1R0_EL1_S, // 612
+ MISCREG_ICC_AP1R1_EL1, // 613
+ MISCREG_ICC_AP1R1_EL1_NS, // 614
+ MISCREG_ICC_AP1R1_EL1_S, // 615
+ MISCREG_ICC_AP1R2_EL1, // 616
+ MISCREG_ICC_AP1R2_EL1_NS, // 617
+ MISCREG_ICC_AP1R2_EL1_S, // 618
+ MISCREG_ICC_AP1R3_EL1, // 619
+ MISCREG_ICC_AP1R3_EL1_NS, // 620
+ MISCREG_ICC_AP1R3_EL1_S, // 621
+ MISCREG_ICC_DIR_EL1, // 622
+ MISCREG_ICC_RPR_EL1, // 623
+ MISCREG_ICC_SGI1R_EL1, // 624
+ MISCREG_ICC_ASGI1R_EL1, // 625
+ MISCREG_ICC_SGI0R_EL1, // 626
+ MISCREG_ICC_IAR1_EL1, // 627
+ MISCREG_ICC_EOIR1_EL1, // 628
+ MISCREG_ICC_HPPIR1_EL1, // 629
+ MISCREG_ICC_BPR1_EL1, // 630
+ MISCREG_ICC_BPR1_EL1_NS, // 631
+ MISCREG_ICC_BPR1_EL1_S, // 632
+ MISCREG_ICC_CTLR_EL1, // 633
+ MISCREG_ICC_CTLR_EL1_NS, // 634
+ MISCREG_ICC_CTLR_EL1_S, // 635
+ MISCREG_ICC_SRE_EL1, // 636
+ MISCREG_ICC_SRE_EL1_NS, // 637
+ MISCREG_ICC_SRE_EL1_S, // 638
+ MISCREG_ICC_IGRPEN0_EL1, // 639
+ MISCREG_ICC_IGRPEN1_EL1, // 640
+ MISCREG_ICC_IGRPEN1_EL1_NS, // 641
+ MISCREG_ICC_IGRPEN1_EL1_S, // 642
+ MISCREG_ICC_SRE_EL2, // 643
+ MISCREG_ICC_CTLR_EL3, // 644
+ MISCREG_ICC_SRE_EL3, // 645
+ MISCREG_ICC_IGRPEN1_EL3, // 646
+
+ // GICv3, CPU interface, virtualization
+ MISCREG_ICH_AP0R0_EL2, // 647
+ MISCREG_ICH_AP0R1_EL2, // 648
+ MISCREG_ICH_AP0R2_EL2, // 649
+ MISCREG_ICH_AP0R3_EL2, // 650
+ MISCREG_ICH_AP1R0_EL2, // 651
+ MISCREG_ICH_AP1R1_EL2, // 652
+ MISCREG_ICH_AP1R2_EL2, // 653
+ MISCREG_ICH_AP1R3_EL2, // 654
+ MISCREG_ICH_HCR_EL2, // 655
+ MISCREG_ICH_VTR_EL2, // 656
+ MISCREG_ICH_MISR_EL2, // 657
+ MISCREG_ICH_EISR_EL2, // 658
+ MISCREG_ICH_ELRSR_EL2, // 659
+ MISCREG_ICH_VMCR_EL2, // 660
+ MISCREG_ICH_LR0_EL2, // 661
+ MISCREG_ICH_LR1_EL2, // 662
+ MISCREG_ICH_LR2_EL2, // 663
+ MISCREG_ICH_LR3_EL2, // 664
+ MISCREG_ICH_LR4_EL2, // 665
+ MISCREG_ICH_LR5_EL2, // 666
+ MISCREG_ICH_LR6_EL2, // 667
+ MISCREG_ICH_LR7_EL2, // 668
+ MISCREG_ICH_LR8_EL2, // 669
+ MISCREG_ICH_LR9_EL2, // 670
+ MISCREG_ICH_LR10_EL2, // 671
+ MISCREG_ICH_LR11_EL2, // 672
+ MISCREG_ICH_LR12_EL2, // 673
+ MISCREG_ICH_LR13_EL2, // 674
+ MISCREG_ICH_LR14_EL2, // 675
+ MISCREG_ICH_LR15_EL2, // 676
+
+ MISCREG_ICV_PMR_EL1, // 677
+ MISCREG_ICV_IAR0_EL1, // 678
+ MISCREG_ICV_EOIR0_EL1, // 679
+ MISCREG_ICV_HPPIR0_EL1, // 680
+ MISCREG_ICV_BPR0_EL1, // 681
+ MISCREG_ICV_AP0R0_EL1, // 682
+ MISCREG_ICV_AP0R1_EL1, // 683
+ MISCREG_ICV_AP0R2_EL1, // 684
+ MISCREG_ICV_AP0R3_EL1, // 685
+ MISCREG_ICV_AP1R0_EL1, // 686
+ MISCREG_ICV_AP1R0_EL1_NS, // 687
+ MISCREG_ICV_AP1R0_EL1_S, // 688
+ MISCREG_ICV_AP1R1_EL1, // 689
+ MISCREG_ICV_AP1R1_EL1_NS, // 690
+ MISCREG_ICV_AP1R1_EL1_S, // 691
+ MISCREG_ICV_AP1R2_EL1, // 692
+ MISCREG_ICV_AP1R2_EL1_NS, // 693
+ MISCREG_ICV_AP1R2_EL1_S, // 694
+ MISCREG_ICV_AP1R3_EL1, // 695
+ MISCREG_ICV_AP1R3_EL1_NS, // 696
+ MISCREG_ICV_AP1R3_EL1_S, // 697
+ MISCREG_ICV_DIR_EL1, // 698
+ MISCREG_ICV_RPR_EL1, // 699
+ MISCREG_ICV_SGI1R_EL1, // 700
+ MISCREG_ICV_ASGI1R_EL1, // 701
+ MISCREG_ICV_SGI0R_EL1, // 702
+ MISCREG_ICV_IAR1_EL1, // 703
+ MISCREG_ICV_EOIR1_EL1, // 704
+ MISCREG_ICV_HPPIR1_EL1, // 705
+ MISCREG_ICV_BPR1_EL1, // 706
+ MISCREG_ICV_BPR1_EL1_NS, // 707
+ MISCREG_ICV_BPR1_EL1_S, // 708
+ MISCREG_ICV_CTLR_EL1, // 709
+ MISCREG_ICV_CTLR_EL1_NS, // 710
+ MISCREG_ICV_CTLR_EL1_S, // 711
+ MISCREG_ICV_SRE_EL1, // 712
+ MISCREG_ICV_SRE_EL1_NS, // 713
+ MISCREG_ICV_SRE_EL1_S, // 714
+ MISCREG_ICV_IGRPEN0_EL1, // 715
+ MISCREG_ICV_IGRPEN1_EL1, // 716
+ MISCREG_ICV_IGRPEN1_EL1_NS, // 717
+ MISCREG_ICV_IGRPEN1_EL1_S, // 718
+
+ MISCREG_ICC_AP0R0, // 719
+ MISCREG_ICC_AP0R1, // 720
+ MISCREG_ICC_AP0R2, // 721
+ MISCREG_ICC_AP0R3, // 722
+ MISCREG_ICC_AP1R0, // 723
+ MISCREG_ICC_AP1R0_NS, // 724
+ MISCREG_ICC_AP1R0_S, // 725
+ MISCREG_ICC_AP1R1, // 726
+ MISCREG_ICC_AP1R1_NS, // 727
+ MISCREG_ICC_AP1R1_S, // 728
+ MISCREG_ICC_AP1R2, // 729
+ MISCREG_ICC_AP1R2_NS, // 730
+ MISCREG_ICC_AP1R2_S, // 731
+ MISCREG_ICC_AP1R3, // 732
+ MISCREG_ICC_AP1R3_NS, // 733
+ MISCREG_ICC_AP1R3_S, // 734
+ MISCREG_ICC_ASGI1R, // 735
+ MISCREG_ICC_BPR0, // 736
+ MISCREG_ICC_BPR1, // 737
+ MISCREG_ICC_BPR1_NS, // 738
+ MISCREG_ICC_BPR1_S, // 739
+ MISCREG_ICC_CTLR, // 740
+ MISCREG_ICC_CTLR_NS, // 741
+ MISCREG_ICC_CTLR_S, // 742
+ MISCREG_ICC_DIR, // 743
+ MISCREG_ICC_EOIR0, // 744
+ MISCREG_ICC_EOIR1, // 745
+ MISCREG_ICC_HPPIR0, // 746
+ MISCREG_ICC_HPPIR1, // 747
+ MISCREG_ICC_HSRE, // 748
+ MISCREG_ICC_IAR0, // 749
+ MISCREG_ICC_IAR1, // 750
+ MISCREG_ICC_IGRPEN0, // 751
+ MISCREG_ICC_IGRPEN1, // 752
+ MISCREG_ICC_IGRPEN1_NS, // 753
+ MISCREG_ICC_IGRPEN1_S, // 754
+ MISCREG_ICC_MCTLR, // 755
+ MISCREG_ICC_MGRPEN1, // 756
+ MISCREG_ICC_MSRE, // 757
+ MISCREG_ICC_PMR, // 758
+ MISCREG_ICC_RPR, // 759
+ MISCREG_ICC_SGI0R, // 760
+ MISCREG_ICC_SGI1R, // 761
+ MISCREG_ICC_SRE, // 762
+ MISCREG_ICC_SRE_NS, // 763
+ MISCREG_ICC_SRE_S, // 764
+
+ MISCREG_ICH_AP0R0, // 765
+ MISCREG_ICH_AP0R1, // 766
+ MISCREG_ICH_AP0R2, // 767
+ MISCREG_ICH_AP0R3, // 768
+ MISCREG_ICH_AP1R0, // 769
+ MISCREG_ICH_AP1R1, // 770
+ MISCREG_ICH_AP1R2, // 771
+ MISCREG_ICH_AP1R3, // 772
+ MISCREG_ICH_HCR, // 773
+ MISCREG_ICH_VTR, // 774
+ MISCREG_ICH_MISR, // 775
+ MISCREG_ICH_EISR, // 776
+ MISCREG_ICH_ELRSR, // 777
+ MISCREG_ICH_VMCR, // 778
+ MISCREG_ICH_LR0, // 779
+ MISCREG_ICH_LR1, // 780
+ MISCREG_ICH_LR2, // 781
+ MISCREG_ICH_LR3, // 782
+ MISCREG_ICH_LR4, // 783
+ MISCREG_ICH_LR5, // 784
+ MISCREG_ICH_LR6, // 785
+ MISCREG_ICH_LR7, // 786
+ MISCREG_ICH_LR8, // 787
+ MISCREG_ICH_LR9, // 788
+ MISCREG_ICH_LR10, // 789
+ MISCREG_ICH_LR11, // 790
+ MISCREG_ICH_LR12, // 791
+ MISCREG_ICH_LR13, // 792
+ MISCREG_ICH_LR14, // 793
+ MISCREG_ICH_LR15, // 794
+ MISCREG_ICH_LRC0, // 795
+ MISCREG_ICH_LRC1, // 796
+ MISCREG_ICH_LRC2, // 797
+ MISCREG_ICH_LRC3, // 798
+ MISCREG_ICH_LRC4, // 799
+ MISCREG_ICH_LRC5, // 800
+ MISCREG_ICH_LRC6, // 801
+ MISCREG_ICH_LRC7, // 802
+ MISCREG_ICH_LRC8, // 803
+ MISCREG_ICH_LRC9, // 804
+ MISCREG_ICH_LRC10, // 805
+ MISCREG_ICH_LRC11, // 806
+ MISCREG_ICH_LRC12, // 807
+ MISCREG_ICH_LRC13, // 808
+ MISCREG_ICH_LRC14, // 809
+ MISCREG_ICH_LRC15, // 810
+
+ MISCREG_CNTHV_CTL_EL2, // 811
+ MISCREG_CNTHV_CVAL_EL2, // 812
+ MISCREG_CNTHV_TVAL_EL2, // 813
+
+ MISCREG_ID_AA64MMFR2_EL1, // 814
// NUM_PHYS_MISCREGS specifies the number of actual physical
// registers, not considering the following pseudo-registers
// (dummy registers), like UNKNOWN, CP15_UNIMPL,
MISCREG_IMPDEF_UNIMPL.
// Checkpointing should use this physical index when
// saving/restoring register values.
- NUM_PHYS_MISCREGS = 606, // 606
+ NUM_PHYS_MISCREGS = 815, // 815
// Dummy registers
MISCREG_NOP,
@@ -1385,11 +1600,228 @@
"contextidr_el2",
"ttbr1_el2",
+
+ // GICv3, CPU interface
+ "icc_pmr_el1",
+ "icc_iar0_el1",
+ "icc_eoir0_el1",
+ "icc_hppir0_el1",
+ "icc_bpr0_el1",
+ "icc_ap0r0_el1",
+ "icc_ap0r1_el1",
+ "icc_ap0r2_el1",
+ "icc_ap0r3_el1",
+ "icc_ap1r0_el1",
+ "icc_ap1r0_el1_ns",
+ "icc_ap1r0_el1_s",
+ "icc_ap1r1_el1",
+ "icc_ap1r1_el1_ns",
+ "icc_ap1r1_el1_s",
+ "icc_ap1r2_el1",
+ "icc_ap1r2_el1_ns",
+ "icc_ap1r2_el1_s",
+ "icc_ap1r3_el1",
+ "icc_ap1r3_el1_ns",
+ "icc_ap1r3_el1_s",
+ "icc_dir_el1",
+ "icc_rpr_el1",
+ "icc_sgi1r_el1",
+ "icc_asgi1r_el1",
+ "icc_sgi0r_el1",
+ "icc_iar1_el1",
+ "icc_eoir1_el1",
+ "icc_hppir1_el1",
+ "icc_bpr1_el1",
+ "icc_bpr1_el1_ns",
+ "icc_bpr1_el1_s",
+ "icc_ctlr_el1",
+ "icc_ctlr_el1_ns",
+ "icc_ctlr_el1_s",
+ "icc_sre_el1",
+ "icc_sre_el1_ns",
+ "icc_sre_el1_s",
+ "icc_igrpen0_el1",
+ "icc_igrpen1_el1",
+ "icc_igrpen1_el1_ns",
+ "icc_igrpen1_el1_s",
+ "icc_sre_el2",
+ "icc_ctlr_el3",
+ "icc_sre_el3",
+ "icc_igrpen1_el3",
+
+ // GICv3, CPU interface, virtualization
+ "ich_ap0r0_el2",
+ "ich_ap0r1_el2",
+ "ich_ap0r2_el2",
+ "ich_ap0r3_el2",
+ "ich_ap1r0_el2",
+ "ich_ap1r1_el2",
+ "ich_ap1r2_el2",
+ "ich_ap1r3_el2",
+ "ich_hcr_el2",
+ "ich_vtr_el2",
+ "ich_misr_el2",
+ "ich_eisr_el2",
+ "ich_elrsr_el2",
+ "ich_vmcr_el2",
+ "ich_lr0_el2",
+ "ich_lr1_el2",
+ "ich_lr2_el2",
+ "ich_lr3_el2",
+ "ich_lr4_el2",
+ "ich_lr5_el2",
+ "ich_lr6_el2",
+ "ich_lr7_el2",
+ "ich_lr8_el2",
+ "ich_lr9_el2",
+ "ich_lr10_el2",
+ "ich_lr11_el2",
+ "ich_lr12_el2",
+ "ich_lr13_el2",
+ "ich_lr14_el2",
+ "ich_lr15_el2",
+
+ "icv_pmr_el1",
+ "icv_iar0_el1",
+ "icv_eoir0_el1",
+ "icv_hppir0_el1",
+ "icv_bpr0_el1",
+ "icv_ap0r0_el1",
+ "icv_ap0r1_el1",
+ "icv_ap0r2_el1",
+ "icv_ap0r3_el1",
+ "icv_ap1r0_el1",
+ "icv_ap1r0_el1_ns",
+ "icv_ap1r0_el1_s",
+ "icv_ap1r1_el1",
+ "icv_ap1r1_el1_ns",
+ "icv_ap1r1_el1_s",
+ "icv_ap1r2_el1",
+ "icv_ap1r2_el1_ns",
+ "icv_ap1r2_el1_s",
+ "icv_ap1r3_el1",
+ "icv_ap1r3_el1_ns",
+ "icv_ap1r3_el1_s",
+ "icv_dir_el1",
+ "icv_rpr_el1",
+ "icv_sgi1r_el1",
+ "icv_asgi1r_el1",
+ "icv_sgi0r_el1",
+ "icv_iar1_el1",
+ "icv_eoir1_el1",
+ "icv_hppir1_el1",
+ "icv_bpr1_el1",
+ "icv_bpr1_el1_ns",
+ "icv_bpr1_el1_s",
+ "icv_ctlr_el1",
+ "icv_ctlr_el1_ns",
+ "icv_ctlr_el1_s",
+ "icv_sre_el1",
+ "icv_sre_el1_ns",
+ "icv_sre_el1_s",
+ "icv_igrpen0_el1",
+ "icv_igrpen1_el1",
+ "icv_igrpen1_el1_ns",
+ "icv_igrpen1_el1_s",
+
+ "icc_ap0r0",
+ "icc_ap0r1",
+ "icc_ap0r2",
+ "icc_ap0r3",
+ "icc_ap1r0",
+ "icc_ap1r0_ns",
+ "icc_ap1r0_s",
+ "icc_ap1r1",
+ "icc_ap1r1_ns",
+ "icc_ap1r1_s",
+ "icc_ap1r2",
+ "icc_ap1r2_ns",
+ "icc_ap1r2_s",
+ "icc_ap1r3",
+ "icc_ap1r3_ns",
+ "icc_ap1r3_s",
+ "icc_asgi1r",
+ "icc_bpr0",
+ "icc_bpr1",
+ "icc_bpr1_ns",
+ "icc_bpr1_s",
+ "icc_ctlr",
+ "icc_ctlr_ns",
+ "icc_ctlr_s",
+ "icc_dir",
+ "icc_eoir0",
+ "icc_eoir1",
+ "icc_hppir0",
+ "icc_hppir1",
+ "icc_hsre",
+ "icc_iar0",
+ "icc_iar1",
+ "icc_igrpen0",
+ "icc_igrpen1",
+ "icc_igrpen1_ns",
+ "icc_igrpen1_s",
+ "icc_mctlr",
+ "icc_mgrpen1",
+ "icc_msre",
+ "icc_pmr",
+ "icc_rpr",
+ "icc_sgi0r",
+ "icc_sgi1r",
+ "icc_sre",
+ "icc_sre_ns",
+ "icc_sre_s",
+
+ "ich_ap0r0",
+ "ich_ap0r1",
+ "ich_ap0r2",
+ "ich_ap0r3",
+ "ich_ap1r0",
+ "ich_ap1r1",
+ "ich_ap1r2",
+ "ich_ap1r3",
+ "ich_hcr",
+ "ich_vtr",
+ "ich_misr",
+ "ich_eisr",
+ "ich_elrsr",
+ "ich_vmcr",
+ "ich_lr0",
+ "ich_lr1",
+ "ich_lr2",
+ "ich_lr3",
+ "ich_lr4",
+ "ich_lr5",
+ "ich_lr6",
+ "ich_lr7",
+ "ich_lr8",
+ "ich_lr9",
+ "ich_lr10",
+ "ich_lr11",
+ "ich_lr12",
+ "ich_lr13",
+ "ich_lr14",
+ "ich_lr15",
+ "ich_lrc0",
+ "ich_lrc1",
+ "ich_lrc2",
+ "ich_lrc3",
+ "ich_lrc4",
+ "ich_lrc5",
+ "ich_lrc6",
+ "ich_lrc7",
+ "ich_lrc8",
+ "ich_lrc9",
+ "ich_lrc10",
+ "ich_lrc11",
+ "ich_lrc12",
+ "ich_lrc13",
+ "ich_lrc14",
+ "ich_lrc15",
+
"cnthv_ctl_el2",
"cnthv_cval_el2",
"cnthv_tval_el2",
"id_aa64mmfr2_el1",
- "freeslot2",
"num_phys_regs",
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0059bd13c9a416803b0d0f2d158c11d856e2990c
Gerrit-Change-Number: 14235
Gerrit-PatchSet: 1
Gerrit-Owner: Jairo Balart <[email protected]>
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