Giacomo Travaglini has uploaded a new patch set (#5) to the change
originally created by Giacomo Gabrielli. (
https://gem5-review.googlesource.com/c/public/gem5/+/13521 )
Change subject: arch-arm: Add initial support for SVE gather/scatter
loads/stores
......................................................................
arch-arm: Add initial support for SVE gather/scatter loads/stores
In addition to the code for implementing decoding and execution of
these instructions, a couple of additional features have been
implemented:
1. a mechanism to skip the memory access part of a load/store
operation - used by gather loads for implementing zeroing
predication;
2. the Arm decoder was augmented in a previous changeset to keep track
of the active SVE vector length - this feature is now used by
gather/scatter operations to determine the right number of microops to
be generated.
Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2
Signed-off-by: Giacomo Gabrielli <[email protected]>
---
M src/arch/arm/decoder.hh
A src/arch/arm/insts/sve_macromem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/registers.hh
M src/arch/isa_parser.py
M src/cpu/base_dyn_inst.hh
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
18 files changed, 1,491 insertions(+), 107 deletions(-)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2
Gerrit-Change-Number: 13521
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newpatchset
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