Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/14466

Change subject: riscv: Get rid of some ISA specific register types.
......................................................................

riscv: Get rid of some ISA specific register types.

Change-Id: Ie812cf1d42536094273ba2ec731c16cca38db100
---
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/isa/formats/standard.isa
M src/arch/riscv/process.cc
M src/arch/riscv/process.hh
M src/arch/riscv/registers.hh
M src/arch/riscv/remote_gdb.hh
11 files changed, 92 insertions(+), 96 deletions(-)



diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index b5f3d07..5385af0 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -109,7 +109,7 @@

         // Set fault cause, privilege, and return PC
         tc->setMiscReg(cause,
- (isInterrupt() << (sizeof(MiscReg) * 4 - 1)) | _code); + (isInterrupt() << (sizeof(uint64_t) * 4 - 1)) | _code);
         tc->setMiscReg(epc, tc->instAddr());
         tc->setMiscReg(tval, trap_value());
         tc->setMiscReg(MISCREG_PRV, prv);
@@ -178,4 +178,4 @@
     tc->syscall(tc->readIntReg(SyscallNumReg), fault);
 }

-} // namespace RiscvISA
\ No newline at end of file
+} // namespace RiscvISA
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index d9cb44c..151bcc2 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -45,7 +45,7 @@
 namespace RiscvISA
 {

-enum FloatException : MiscReg {
+enum FloatException : uint64_t {
     FloatInexact = 0x1,
     FloatUnderflow = 0x2,
     FloatOverflow = 0x4,
@@ -53,7 +53,7 @@
     FloatInvalid = 0x10
 };

-enum ExceptionCode : MiscReg {
+enum ExceptionCode : uint64_t {
     INST_ADDR_MISALIGNED = 0,
     INST_ACCESS = 1,
     INST_ILLEGAL = 2,
@@ -87,7 +87,7 @@
     FaultName name() const override { return _name; }
     bool isInterrupt() const { return _interrupt; }
     ExceptionCode exception() const { return _code; }
-    virtual MiscReg trap_value() const { return 0; }
+    virtual RegVal trap_value() const { return 0; }

     virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
     void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
@@ -125,7 +125,7 @@
         : RiscvFault(n, false, INST_ILLEGAL), _inst(inst)
     {}

-    MiscReg trap_value() const override { return _inst; }
+    RegVal trap_value() const override { return _inst; }
 };

 class UnknownInstFault : public InstFault
@@ -189,7 +189,7 @@
         : RiscvFault("Address", false, code), _addr(addr)
     {}

-    MiscReg trap_value() const override { return _addr; }
+    RegVal trap_value() const override { return _addr; }
 };

 class BreakpointFault : public RiscvFault
@@ -202,7 +202,7 @@
         : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc)
     {}

-    MiscReg trap_value() const override { return pcState.pc(); }
+    RegVal trap_value() const override { return pcState.pc(); }
     void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
 };

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 40b18e8..9d3a3c9 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -95,7 +95,7 @@
     return (miscRegFile[counteren] & (1ULL << (hpmcounter))) > 0;
 }

-MiscReg
+RegVal
 ISA::readMiscRegNoEffect(int misc_reg) const
 {
     if (misc_reg > NumMiscRegs || misc_reg < 0) {
@@ -108,7 +108,7 @@
     return miscRegFile[misc_reg];
 }

-MiscReg
+RegVal
 ISA::readMiscReg(int misc_reg, ThreadContext *tc)
 {
     switch (misc_reg) {
@@ -158,7 +158,7 @@
 }

 void
-ISA::setMiscRegNoEffect(int misc_reg, MiscReg val)
+ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
 {
     if (misc_reg > NumMiscRegs || misc_reg < 0) {
         // Illegal CSR
@@ -169,7 +169,7 @@
 }

 void
-ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
 {
     if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
         // Ignore writes to HPM counters for now
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 2602f6d..b1781af 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -65,7 +65,7 @@
 class ISA : public SimObject
 {
   protected:
-    std::vector<MiscReg> miscRegFile;
+    std::vector<RegVal> miscRegFile;

     bool hpmCounterEnabled(int counter) const;

@@ -74,10 +74,10 @@

     void clear();

-    MiscReg readMiscRegNoEffect(int misc_reg) const;
-    MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
-    void setMiscRegNoEffect(int misc_reg, MiscReg val);
-    void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc);
+    RegVal readMiscRegNoEffect(int misc_reg) const;
+    RegVal readMiscReg(int misc_reg, ThreadContext *tc);
+    void setMiscRegNoEffect(int misc_reg, RegVal val);
+    void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);

     RegId flattenRegId(const RegId &regId) const { return regId; }
     int flattenIntIndex(int reg) const { return reg; }
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 0c1d772..5acba6e 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -781,7 +781,7 @@
                     }});
                     0x1: divuw({{
                         if (Rs2_uw == 0) {
-                            Rd_sd = numeric_limits<IntReg>::max();
+                            Rd_sd = numeric_limits<uint64_t>::max();
                         } else {
                             Rd_sd = (int32_t)(Rs1_uw/Rs2_uw);
                         }
diff --git a/src/arch/riscv/isa/formats/fp.isa b/src/arch/riscv/isa/formats/fp.isa
index 5f06721..1047285 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -91,7 +91,7 @@
             }

             if (fault == NoFault) {
-                MiscReg FFLAGS = xc->readMiscReg(MISCREG_FFLAGS);
+                RegVal FFLAGS = xc->readMiscReg(MISCREG_FFLAGS);
                 std::feclearexcept(FE_ALL_EXCEPT);
                 %(code)s;
                 if (std::fetestexcept(FE_INEXACT)) {
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index e9539fe..1391807 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -220,7 +220,7 @@
         %(op_decl)s;
         %(op_rd)s;

-        MiscReg data, olddata;
+        RegVal data, olddata;
         switch (csr) {
           case CSR_FCSR:
             olddata = xc->readMiscReg(MISCREG_FFLAGS) |
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 4e97fcf..7548c65 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -219,12 +219,12 @@
     memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
 }

-RiscvISA::IntReg
+RegVal
 RiscvProcess::getSyscallArg(ThreadContext *tc, int &i)
 {
     // If a larger index is requested than there are syscall argument
     // registers, return 0
-    RiscvISA::IntReg retval = 0;
+    RegVal retval = 0;
     if (i < SyscallArgumentRegs.size())
         retval = tc->readIntReg(SyscallArgumentRegs[i]);
     i++;
@@ -232,7 +232,7 @@
 }

 void
-RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val)
+RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
 {
     tc->setIntReg(SyscallArgumentRegs[i], val);
 }
diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh
index bda278e..8b934b1 100644
--- a/src/arch/riscv/process.hh
+++ b/src/arch/riscv/process.hh
@@ -54,11 +54,10 @@
     void argsInit(int pageSize);

   public:
-    RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override;
+    RegVal getSyscallArg(ThreadContext *tc, int &i) override;
     /// Explicitly import the otherwise hidden getSyscallArg
     using Process::getSyscallArg;
-    void setSyscallArg(ThreadContext *tc, int i,
-                       RiscvISA::IntReg val) override;
+    void setSyscallArg(ThreadContext *tc, int i, RegVal val) override;
     void setSyscallReturn(ThreadContext *tc,
                           SyscallReturn return_value) override;

diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 1dbb92f..fa0614a 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -63,10 +63,7 @@
 using RiscvISAInst::MaxInstDestRegs;
 const int MaxMiscDestRegs = 1;

-typedef RegVal IntReg;
-typedef RegVal FloatReg;
 typedef uint8_t CCReg; // Not applicable to Riscv
-typedef RegVal MiscReg;

 // dummy typedefs since we don't have vector regs
 const unsigned NumVecElemPerVecReg = 2;
@@ -629,76 +626,76 @@
     Bitfield<0> usi;
 EndBitUnion(INTERRUPT)

-const off_t MXL_OFFSET = (sizeof(MiscReg) * 8 - 2);
+const off_t MXL_OFFSET = (sizeof(uint64_t) * 8 - 2);
 const off_t SXL_OFFSET = 34;
 const off_t UXL_OFFSET = 32;
 const off_t FS_OFFSET = 13;
 const off_t FRM_OFFSET = 5;

-const MiscReg ISA_MXL_MASK = 3ULL << MXL_OFFSET;
-const MiscReg ISA_EXT_MASK = mask(26);
-const MiscReg MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;
+const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET;
+const RegVal ISA_EXT_MASK = mask(26);
+const RegVal MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;

-const MiscReg STATUS_SD_MASK = 1ULL << ((sizeof(MiscReg) * 8) - 1);
-const MiscReg STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
-const MiscReg STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
-const MiscReg STATUS_TSR_MASK = 1ULL << 22;
-const MiscReg STATUS_TW_MASK = 1ULL << 21;
-const MiscReg STATUS_TVM_MASK = 1ULL << 20;
-const MiscReg STATUS_MXR_MASK = 1ULL << 19;
-const MiscReg STATUS_SUM_MASK = 1ULL << 18;
-const MiscReg STATUS_MPRV_MASK = 1ULL << 17;
-const MiscReg STATUS_XS_MASK = 3ULL << 15;
-const MiscReg STATUS_FS_MASK = 3ULL << FS_OFFSET;
-const MiscReg STATUS_MPP_MASK = 3ULL << 11;
-const MiscReg STATUS_SPP_MASK = 1ULL << 8;
-const MiscReg STATUS_MPIE_MASK = 1ULL << 7;
-const MiscReg STATUS_SPIE_MASK = 1ULL << 5;
-const MiscReg STATUS_UPIE_MASK = 1ULL << 4;
-const MiscReg STATUS_MIE_MASK = 1ULL << 3;
-const MiscReg STATUS_SIE_MASK = 1ULL << 1;
-const MiscReg STATUS_UIE_MASK = 1ULL << 0;
-const MiscReg MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK |
-                             STATUS_UXL_MASK | STATUS_TSR_MASK |
-                             STATUS_TW_MASK | STATUS_TVM_MASK |
-                             STATUS_MXR_MASK | STATUS_SUM_MASK |
-                             STATUS_MPRV_MASK | STATUS_XS_MASK |
-                             STATUS_FS_MASK | STATUS_MPP_MASK |
-                             STATUS_SPP_MASK | STATUS_MPIE_MASK |
-                             STATUS_SPIE_MASK | STATUS_UPIE_MASK |
-                             STATUS_MIE_MASK | STATUS_SIE_MASK |
-                             STATUS_UIE_MASK;
-const MiscReg SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
-                             STATUS_MXR_MASK | STATUS_SUM_MASK |
-                             STATUS_XS_MASK | STATUS_FS_MASK |
-                             STATUS_SPP_MASK | STATUS_SPIE_MASK |
-                             STATUS_UPIE_MASK | STATUS_SIE_MASK |
-                             STATUS_UIE_MASK;
-const MiscReg USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
-                             STATUS_SUM_MASK | STATUS_XS_MASK |
-                             STATUS_FS_MASK | STATUS_UPIE_MASK |
-                             STATUS_UIE_MASK;
+const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1);
+const RegVal STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
+const RegVal STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
+const RegVal STATUS_TSR_MASK = 1ULL << 22;
+const RegVal STATUS_TW_MASK = 1ULL << 21;
+const RegVal STATUS_TVM_MASK = 1ULL << 20;
+const RegVal STATUS_MXR_MASK = 1ULL << 19;
+const RegVal STATUS_SUM_MASK = 1ULL << 18;
+const RegVal STATUS_MPRV_MASK = 1ULL << 17;
+const RegVal STATUS_XS_MASK = 3ULL << 15;
+const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET;
+const RegVal STATUS_MPP_MASK = 3ULL << 11;
+const RegVal STATUS_SPP_MASK = 1ULL << 8;
+const RegVal STATUS_MPIE_MASK = 1ULL << 7;
+const RegVal STATUS_SPIE_MASK = 1ULL << 5;
+const RegVal STATUS_UPIE_MASK = 1ULL << 4;
+const RegVal STATUS_MIE_MASK = 1ULL << 3;
+const RegVal STATUS_SIE_MASK = 1ULL << 1;
+const RegVal STATUS_UIE_MASK = 1ULL << 0;
+const RegVal MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK |
+                            STATUS_UXL_MASK | STATUS_TSR_MASK |
+                            STATUS_TW_MASK | STATUS_TVM_MASK |
+                            STATUS_MXR_MASK | STATUS_SUM_MASK |
+                            STATUS_MPRV_MASK | STATUS_XS_MASK |
+                            STATUS_FS_MASK | STATUS_MPP_MASK |
+                            STATUS_SPP_MASK | STATUS_MPIE_MASK |
+                            STATUS_SPIE_MASK | STATUS_UPIE_MASK |
+                            STATUS_MIE_MASK | STATUS_SIE_MASK |
+                            STATUS_UIE_MASK;
+const RegVal SSTATUS_MASK = STATUS_SD_MASK | STATUS_UXL_MASK |
+                            STATUS_MXR_MASK | STATUS_SUM_MASK |
+                            STATUS_XS_MASK | STATUS_FS_MASK |
+                            STATUS_SPP_MASK | STATUS_SPIE_MASK |
+                            STATUS_UPIE_MASK | STATUS_SIE_MASK |
+                            STATUS_UIE_MASK;
+const RegVal USTATUS_MASK = STATUS_SD_MASK | STATUS_MXR_MASK |
+                            STATUS_SUM_MASK | STATUS_XS_MASK |
+                            STATUS_FS_MASK | STATUS_UPIE_MASK |
+                            STATUS_UIE_MASK;

-const MiscReg MEI_MASK = 1ULL << 11;
-const MiscReg SEI_MASK = 1ULL << 9;
-const MiscReg UEI_MASK = 1ULL << 8;
-const MiscReg MTI_MASK = 1ULL << 7;
-const MiscReg STI_MASK = 1ULL << 5;
-const MiscReg UTI_MASK = 1ULL << 4;
-const MiscReg MSI_MASK = 1ULL << 3;
-const MiscReg SSI_MASK = 1ULL << 1;
-const MiscReg USI_MASK = 1ULL << 0;
-const MiscReg MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK |
-                        MTI_MASK | STI_MASK | UTI_MASK |
-                        MSI_MASK | SSI_MASK | USI_MASK;
-const MiscReg SI_MASK = SEI_MASK | UEI_MASK |
-                        STI_MASK | UTI_MASK |
-                        SSI_MASK | USI_MASK;
-const MiscReg UI_MASK = UEI_MASK | UTI_MASK | USI_MASK;
-const MiscReg FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
-const MiscReg FRM_MASK = 0x7;
+const RegVal MEI_MASK = 1ULL << 11;
+const RegVal SEI_MASK = 1ULL << 9;
+const RegVal UEI_MASK = 1ULL << 8;
+const RegVal MTI_MASK = 1ULL << 7;
+const RegVal STI_MASK = 1ULL << 5;
+const RegVal UTI_MASK = 1ULL << 4;
+const RegVal MSI_MASK = 1ULL << 3;
+const RegVal SSI_MASK = 1ULL << 1;
+const RegVal USI_MASK = 1ULL << 0;
+const RegVal MI_MASK = MEI_MASK | SEI_MASK | UEI_MASK |
+                       MTI_MASK | STI_MASK | UTI_MASK |
+                       MSI_MASK | SSI_MASK | USI_MASK;
+const RegVal SI_MASK = SEI_MASK | UEI_MASK |
+                       STI_MASK | UTI_MASK |
+                       SSI_MASK | USI_MASK;
+const RegVal UI_MASK = UEI_MASK | UTI_MASK | USI_MASK;
+const RegVal FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
+const RegVal FRM_MASK = 0x7;

-const std::map<int, MiscReg> CSRMasks = {
+const std::map<int, RegVal> CSRMasks = {
     {CSR_USTATUS, USTATUS_MASK},
     {CSR_UIE, UI_MASK},
     {CSR_UIP, UI_MASK},
diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index adb438d..7fcb28d 100644
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -59,15 +59,15 @@
       using BaseGdbRegCache::BaseGdbRegCache;
       private:
         struct {
-            IntReg gpr[NumIntArchRegs];
-            IntReg pc;
-            FloatReg fpr[NumFloatRegs];
+            uint64_t gpr[NumIntArchRegs];
+            uint64_t pc;
+            uint64_t fpr[NumFloatRegs];

-            MiscReg csr_base;
+            uint64_t csr_base;
             uint32_t fflags;
             uint32_t frm;
             uint32_t fcsr;
-            MiscReg csr[NumMiscRegs - ExplicitCSRs];
+            uint64_t csr[NumMiscRegs - ExplicitCSRs];
         } __attribute__((__packed__)) r;
       public:
         char *data() const { return (char *)&r; }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie812cf1d42536094273ba2ec731c16cca38db100
Gerrit-Change-Number: 14466
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-MessageType: newchange
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