[gem5-dev] Change in gem5/gem5[master]: mem-cache: Use header delay on latency calculation

[Daniel Carvalho (Gerrit)]

Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/14876

Change subject: mem-cache: Use header delay on latency calculation
......................................................................

mem-cache: Use header delay on latency calculation

Previously the bus delay was being ignored for the access latency
calculation, and then applied on top of the access latency. This
patch fixes the order, as first the packet must arrive before the
access starts.

Change-Id: I6d55299a911d54625c147814dd423bfc63ef1b65
Signed-off-by: Daniel R. Carvalho <oda...@yahoo.com.br>
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
2 files changed, 11 insertions(+), 8 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 15e5c76..5065a40 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -360,7 +360,7 @@
     // The latency charged is just the value set by the access() function.
     // In case of a hit we are neglecting response latency.
     // In case of a miss we are neglecting forward latency.
-    Tick request_time = clockEdge(lat) + pkt->headerDelay;
+    Tick request_time = clockEdge(lat);
     // Here we reset the timing of the packet.
     pkt->headerDelay = pkt->payloadDelay = 0;

@@ -883,7 +883,7 @@
 //
 /////////////////////////////////////////////////////
 Cycles
-BaseCache::calculateAccessLatency(const CacheBlk* blk,
+BaseCache::calculateAccessLatency(const CacheBlk* blk, const Tick tick,
                                   const Cycles lookup_lat) const
 {
     Cycles lat(lookup_lat);
@@ -900,9 +900,9 @@
         // Check if the block to be accessed is available. If not, apply  
the
         // access latency on top of when the block is ready to be accessed.
         const Tick when_ready = blk->getWhenReady();
-        if (when_ready > curTick() &&
-            ticksToCycles(when_ready - curTick()) > lat) {
-            lat += ticksToCycles(when_ready - curTick());
+        if (when_ready > tick &&
+            ticksToCycles(when_ready - tick) > lat) {
+            lat += ticksToCycles(when_ready - tick);
         }
     }

@@ -924,8 +924,10 @@
     Cycles tag_latency(0);
     blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), tag_latency);

-    // Calculate access latency
-    lat = calculateAccessLatency(blk, tag_latency);
+    // Calculate access latency on top of when the packet arrives. This
+    // takes into account the bus delay.
+    lat = calculateAccessLatency(blk, curTick() + pkt->headerDelay,
+                                 tag_latency);

     DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(),
             blk ? "hit " + blk->print() : "miss");
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 240bf21..a64df29 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -423,10 +423,11 @@
      * whether access was a hit or miss.
      *
      * @param blk The cache block that was accessed.
+     * @param tick The Tick at which the packet arrived (without payload).
      * @param lookup_lat Latency of the respective tag lookup.
      * @return The number of ticks that pass due to a block access.
      */
-    Cycles calculateAccessLatency(const CacheBlk* blk,
+    Cycles calculateAccessLatency(const CacheBlk* blk, const Tick tick,
                                   const Cycles lookup_lat) const;

     /**

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I6d55299a911d54625c147814dd423bfc63ef1b65
Gerrit-Change-Number: 14876
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-MessageType: newchange
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