Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/15138
Change subject: arch-arm: implement the GDB XML target description for ARM
......................................................................
arch-arm: implement the GDB XML target description for ARM
The supported registers are essentially the same as before this patch,
but it is now trivial to make new registers visible in future commits.
The XML files were copied from the binutils-gdb source tree under
gdb/features at commit 4ba1087183b5a5a9de8b56bb86a2fb902501baf2 Those
XML files have a different copyright header than the rest of
binutils-gdb which allows them to be copied into non-GPL projects.
Change-Id: Id15b7aeccca824c342e49a626d2877179474f3d4
---
M SConstruct
A ext/gdb-xml/aarch64-core.xml
A ext/gdb-xml/aarch64-fpu.xml
A ext/gdb-xml/aarch64-target.xml
A ext/gdb-xml/arm-core.xml
A ext/gdb-xml/arm-target.xml
A ext/gdb-xml/arm-vfpv3.xml
M src/SConscript
M src/arch/arm/SConscript
M src/arch/arm/remote_gdb.cc
M src/arch/arm/remote_gdb.hh
11 files changed, 347 insertions(+), 6 deletions(-)
diff --git a/SConstruct b/SConstruct
index 0a8cd0e..4180218 100755
--- a/SConstruct
+++ b/SConstruct
@@ -1079,6 +1079,9 @@
main.SConscript(joinpath(root, 'SConscript'),
variant_dir=joinpath(build_root, build_dir))
+gdb_xml_dir = joinpath(ext_dir, 'gdb-xml')
+Export('gdb_xml_dir')
+
main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
###################################################
diff --git a/ext/gdb-xml/aarch64-core.xml b/ext/gdb-xml/aarch64-core.xml
new file mode 100644
index 0000000..eb6364e
--- /dev/null
+++ b/ext/gdb-xml/aarch64-core.xml
@@ -0,0 +1,67 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2009-2018 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.aarch64.core">
+ <reg name="x0" bitsize="64"/>
+ <reg name="x1" bitsize="64"/>
+ <reg name="x2" bitsize="64"/>
+ <reg name="x3" bitsize="64"/>
+ <reg name="x4" bitsize="64"/>
+ <reg name="x5" bitsize="64"/>
+ <reg name="x6" bitsize="64"/>
+ <reg name="x7" bitsize="64"/>
+ <reg name="x8" bitsize="64"/>
+ <reg name="x9" bitsize="64"/>
+ <reg name="x10" bitsize="64"/>
+ <reg name="x11" bitsize="64"/>
+ <reg name="x12" bitsize="64"/>
+ <reg name="x13" bitsize="64"/>
+ <reg name="x14" bitsize="64"/>
+ <reg name="x15" bitsize="64"/>
+ <reg name="x16" bitsize="64"/>
+ <reg name="x17" bitsize="64"/>
+ <reg name="x18" bitsize="64"/>
+ <reg name="x19" bitsize="64"/>
+ <reg name="x20" bitsize="64"/>
+ <reg name="x21" bitsize="64"/>
+ <reg name="x22" bitsize="64"/>
+ <reg name="x23" bitsize="64"/>
+ <reg name="x24" bitsize="64"/>
+ <reg name="x25" bitsize="64"/>
+ <reg name="x26" bitsize="64"/>
+ <reg name="x27" bitsize="64"/>
+ <reg name="x28" bitsize="64"/>
+ <reg name="x29" bitsize="64"/>
+ <reg name="x30" bitsize="64"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+
+ <flags id="cpsr_flags" size="4">
+ <field name="SP" start="0" end="0"/>
+ <field name="" start="1" end="1"/>
+ <field name="EL" start="2" end="3"/>
+ <field name="nRW" start="4" end="4"/>
+ <field name="" start="5" end="5"/>
+ <field name="F" start="6" end="6"/>
+ <field name="I" start="7" end="7"/>
+ <field name="A" start="8" end="8"/>
+ <field name="D" start="9" end="9"/>
+
+ <field name="IL" start="20" end="20"/>
+ <field name="SS" start="21" end="21"/>
+
+ <field name="V" start="28" end="28"/>
+ <field name="C" start="29" end="29"/>
+ <field name="Z" start="30" end="30"/>
+ <field name="N" start="31" end="31"/>
+ </flags>
+ <reg name="cpsr" bitsize="32" type="cpsr_flags"/>
+
+</feature>
diff --git a/ext/gdb-xml/aarch64-fpu.xml b/ext/gdb-xml/aarch64-fpu.xml
new file mode 100644
index 0000000..399099a
--- /dev/null
+++ b/ext/gdb-xml/aarch64-fpu.xml
@@ -0,0 +1,86 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2009-2018 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.aarch64.fpu">
+ <vector id="v2d" type="ieee_double" count="2"/>
+ <vector id="v2u" type="uint64" count="2"/>
+ <vector id="v2i" type="int64" count="2"/>
+ <vector id="v4f" type="ieee_single" count="4"/>
+ <vector id="v4u" type="uint32" count="4"/>
+ <vector id="v4i" type="int32" count="4"/>
+ <vector id="v8u" type="uint16" count="8"/>
+ <vector id="v8i" type="int16" count="8"/>
+ <vector id="v16u" type="uint8" count="16"/>
+ <vector id="v16i" type="int8" count="16"/>
+ <vector id="v1u" type="uint128" count="1"/>
+ <vector id="v1i" type="int128" count="1"/>
+ <union id="vnd">
+ <field name="f" type="v2d"/>
+ <field name="u" type="v2u"/>
+ <field name="s" type="v2i"/>
+ </union>
+ <union id="vns">
+ <field name="f" type="v4f"/>
+ <field name="u" type="v4u"/>
+ <field name="s" type="v4i"/>
+ </union>
+ <union id="vnh">
+ <field name="u" type="v8u"/>
+ <field name="s" type="v8i"/>
+ </union>
+ <union id="vnb">
+ <field name="u" type="v16u"/>
+ <field name="s" type="v16i"/>
+ </union>
+ <union id="vnq">
+ <field name="u" type="v1u"/>
+ <field name="s" type="v1i"/>
+ </union>
+ <union id="aarch64v">
+ <field name="d" type="vnd"/>
+ <field name="s" type="vns"/>
+ <field name="h" type="vnh"/>
+ <field name="b" type="vnb"/>
+ <field name="q" type="vnq"/>
+ </union>
+ <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/>
+ <reg name="v1" bitsize="128" type="aarch64v" />
+ <reg name="v2" bitsize="128" type="aarch64v" />
+ <reg name="v3" bitsize="128" type="aarch64v" />
+ <reg name="v4" bitsize="128" type="aarch64v" />
+ <reg name="v5" bitsize="128" type="aarch64v" />
+ <reg name="v6" bitsize="128" type="aarch64v" />
+ <reg name="v7" bitsize="128" type="aarch64v" />
+ <reg name="v8" bitsize="128" type="aarch64v" />
+ <reg name="v9" bitsize="128" type="aarch64v" />
+ <reg name="v10" bitsize="128" type="aarch64v"/>
+ <reg name="v11" bitsize="128" type="aarch64v"/>
+ <reg name="v12" bitsize="128" type="aarch64v"/>
+ <reg name="v13" bitsize="128" type="aarch64v"/>
+ <reg name="v14" bitsize="128" type="aarch64v"/>
+ <reg name="v15" bitsize="128" type="aarch64v"/>
+ <reg name="v16" bitsize="128" type="aarch64v"/>
+ <reg name="v17" bitsize="128" type="aarch64v"/>
+ <reg name="v18" bitsize="128" type="aarch64v"/>
+ <reg name="v19" bitsize="128" type="aarch64v"/>
+ <reg name="v20" bitsize="128" type="aarch64v"/>
+ <reg name="v21" bitsize="128" type="aarch64v"/>
+ <reg name="v22" bitsize="128" type="aarch64v"/>
+ <reg name="v23" bitsize="128" type="aarch64v"/>
+ <reg name="v24" bitsize="128" type="aarch64v"/>
+ <reg name="v25" bitsize="128" type="aarch64v"/>
+ <reg name="v26" bitsize="128" type="aarch64v"/>
+ <reg name="v27" bitsize="128" type="aarch64v"/>
+ <reg name="v28" bitsize="128" type="aarch64v"/>
+ <reg name="v29" bitsize="128" type="aarch64v"/>
+ <reg name="v30" bitsize="128" type="aarch64v"/>
+ <reg name="v31" bitsize="128" type="aarch64v"/>
+ <reg name="fpsr" bitsize="32"/>
+ <reg name="fpcr" bitsize="32"/>
+</feature>
diff --git a/ext/gdb-xml/aarch64-target.xml b/ext/gdb-xml/aarch64-target.xml
new file mode 100644
index 0000000..2b87cd3
--- /dev/null
+++ b/ext/gdb-xml/aarch64-target.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2009-2018 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>aarch64</architecture>
+ <xi:include href="aarch64-core.xml"/>
+ <xi:include href="aarch64-fpu.xml"/>
+</target>
diff --git a/ext/gdb-xml/arm-core.xml b/ext/gdb-xml/arm-core.xml
new file mode 100644
index 0000000..dc9b3cf
--- /dev/null
+++ b/ext/gdb-xml/arm-core.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2007-2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.arm.core">
+ <reg name="r0" bitsize="32" type="uint32"/>
+ <reg name="r1" bitsize="32" type="uint32"/>
+ <reg name="r2" bitsize="32" type="uint32"/>
+ <reg name="r3" bitsize="32" type="uint32"/>
+ <reg name="r4" bitsize="32" type="uint32"/>
+ <reg name="r5" bitsize="32" type="uint32"/>
+ <reg name="r6" bitsize="32" type="uint32"/>
+ <reg name="r7" bitsize="32" type="uint32"/>
+ <reg name="r8" bitsize="32" type="uint32"/>
+ <reg name="r9" bitsize="32" type="uint32"/>
+ <reg name="r10" bitsize="32" type="uint32"/>
+ <reg name="r11" bitsize="32" type="uint32"/>
+ <reg name="r12" bitsize="32" type="uint32"/>
+ <reg name="sp" bitsize="32" type="data_ptr"/>
+ <reg name="lr" bitsize="32"/>
+ <reg name="pc" bitsize="32" type="code_ptr"/>
+
+ <!-- The CPSR is register 25, rather than register 16, because
+ the FPA registers historically were placed between the PC
+ and the CPSR in the "g" packet. -->
+ <reg name="cpsr" bitsize="32" regnum="25"/>
+</feature>
diff --git a/ext/gdb-xml/arm-target.xml b/ext/gdb-xml/arm-target.xml
new file mode 100644
index 0000000..6818cac
--- /dev/null
+++ b/ext/gdb-xml/arm-target.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2009-2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>arm</architecture>
+ <xi:include href="arm-core.xml"/>
+ <xi:include href="arm-vfpv3.xml"/>
+ <feature name="org.gnu.gdb.arm.neon"/>
+</target>
diff --git a/ext/gdb-xml/arm-vfpv3.xml b/ext/gdb-xml/arm-vfpv3.xml
new file mode 100644
index 0000000..37e136f
--- /dev/null
+++ b/ext/gdb-xml/arm-vfpv3.xml
@@ -0,0 +1,44 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2009-2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.arm.vfp">
+ <reg name="d0" bitsize="64" type="ieee_double"/>
+ <reg name="d1" bitsize="64" type="ieee_double"/>
+ <reg name="d2" bitsize="64" type="ieee_double"/>
+ <reg name="d3" bitsize="64" type="ieee_double"/>
+ <reg name="d4" bitsize="64" type="ieee_double"/>
+ <reg name="d5" bitsize="64" type="ieee_double"/>
+ <reg name="d6" bitsize="64" type="ieee_double"/>
+ <reg name="d7" bitsize="64" type="ieee_double"/>
+ <reg name="d8" bitsize="64" type="ieee_double"/>
+ <reg name="d9" bitsize="64" type="ieee_double"/>
+ <reg name="d10" bitsize="64" type="ieee_double"/>
+ <reg name="d11" bitsize="64" type="ieee_double"/>
+ <reg name="d12" bitsize="64" type="ieee_double"/>
+ <reg name="d13" bitsize="64" type="ieee_double"/>
+ <reg name="d14" bitsize="64" type="ieee_double"/>
+ <reg name="d15" bitsize="64" type="ieee_double"/>
+ <reg name="d16" bitsize="64" type="ieee_double"/>
+ <reg name="d17" bitsize="64" type="ieee_double"/>
+ <reg name="d18" bitsize="64" type="ieee_double"/>
+ <reg name="d19" bitsize="64" type="ieee_double"/>
+ <reg name="d20" bitsize="64" type="ieee_double"/>
+ <reg name="d21" bitsize="64" type="ieee_double"/>
+ <reg name="d22" bitsize="64" type="ieee_double"/>
+ <reg name="d23" bitsize="64" type="ieee_double"/>
+ <reg name="d24" bitsize="64" type="ieee_double"/>
+ <reg name="d25" bitsize="64" type="ieee_double"/>
+ <reg name="d26" bitsize="64" type="ieee_double"/>
+ <reg name="d27" bitsize="64" type="ieee_double"/>
+ <reg name="d28" bitsize="64" type="ieee_double"/>
+ <reg name="d29" bitsize="64" type="ieee_double"/>
+ <reg name="d30" bitsize="64" type="ieee_double"/>
+ <reg name="d31" bitsize="64" type="ieee_double"/>
+
+ <reg name="fpscr" bitsize="32" type="int" group="float"/>
+</feature>
diff --git a/src/SConscript b/src/SConscript
old mode 100755
new mode 100644
index d4ecf36..83fe6b6
--- a/src/SConscript
+++ b/src/SConscript
@@ -272,6 +272,9 @@
MakeAction(embedBlob, Transform("EMBED BLOB")))
Source(cpp_path)
+def GdbXml(xml_id, header, symbol):
+ Blob(joinpath(gdb_xml_dir, xml_id), header, symbol)
+
class Source(SourceFile):
ungrouped_tag = 'No link group'
source_groups = set()
@@ -501,6 +504,7 @@
# Children should have access
Export('Blob')
+Export('GdbXml')
Export('Source')
Export('PySource')
Export('SimObject')
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index c84c69b..bd1a08f 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -105,3 +105,12 @@
# Add files generated by the ISA description.
ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6)
+
+ header = 'arch/arm/remote_gdb.hh'
+ klass = 'ArmISA::RemoteGDB::'
+ GdbXml('arm-target.xml', klass + 'gdb_xml_arm_target', header)
+ GdbXml('arm-core.xml', klass + 'gdb_xml_arm_core', header)
+ GdbXml('arm-vfpv3.xml', klass + 'gdb_xml_arm_vfpv3', header)
+ GdbXml('aarch64-target.xml', klass + 'gdb_xml_aarch64_target', header)
+ GdbXml('aarch64-core.xml', klass + 'gdb_xml_aarch64_core', header)
+ GdbXml('aarch64-fpu.xml', klass + 'gdb_xml_aarch64_fpu', header)
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index f3ffa85..c54d0a3 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -1,7 +1,7 @@
/*
* Copyright 2015 LabWare
* Copyright 2014 Google Inc.
- * Copyright (c) 2010, 2013, 2016 ARM Limited
+ * Copyright (c) 2010, 2013, 2016, 2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -211,6 +211,8 @@
base++;
}
}
+ r.fpsr = context->readMiscRegNoEffect(MISCREG_FPSR);
+ r.fpcr = context->readMiscRegNoEffect(MISCREG_FPCR);
}
void
@@ -238,6 +240,8 @@
base++;
}
}
+ context->setMiscRegNoEffect(MISCREG_FPSR, r.fpsr);
+ context->setMiscRegNoEffect(MISCREG_FPCR, r.fpcr);
}
void
@@ -261,12 +265,12 @@
r.gpr[13] = context->readIntReg(INTREG_SP);
r.gpr[14] = context->readIntReg(INTREG_LR);
r.gpr[15] = context->pcState().pc();
+ r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
// One day somebody will implement transfer of FPRs correctly.
- for (int i=0; i<8*3; i++) r.fpr[i] = 0;
+ for (int i=0; i<32; i++) r.fpr[i] = 0;
r.fpscr = context->readMiscRegNoEffect(MISCREG_FPSCR);
- r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
}
void
@@ -299,6 +303,51 @@
context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr);
}
+bool
+RemoteGDB::getAnnex(const std::string& annex, std::string& output)
+{
+ static const std::map<std::string, std::string> annexMap32{
+ {
+ "target.xml",
+ std::string(reinterpret_cast<char const*>(gdb_xml_arm_target),
+ gdb_xml_arm_target_len)
+ },
+ {
+ "arm-core.xml",
+ std::string(reinterpret_cast<char const*>(gdb_xml_arm_core),
+ gdb_xml_arm_core_len)
+ },
+ {
+ "arm-vfpv3.xml",
+ std::string(reinterpret_cast<char const*>(gdb_xml_arm_vfpv3),
+ gdb_xml_arm_vfpv3_len)
+ },
+ };
+ static const std::map<std::string, std::string> annexMap64{
+ {
+ "target.xml",
+ std::string(reinterpret_cast<char
const*>(gdb_xml_aarch64_target),
+ gdb_xml_aarch64_target_len)
+ },
+ {
+ "aarch64-core.xml",
+ std::string(reinterpret_cast<char
const*>(gdb_xml_aarch64_core),
+ gdb_xml_aarch64_core_len)
+ },
+ {
+ "aarch64-fpu.xml",
+ std::string(reinterpret_cast<char const*>(gdb_xml_aarch64_fpu),
+ gdb_xml_aarch64_fpu_len)
+ }
+ };
+ auto& annexMap = inAArch64(context()) ? annexMap64 : annexMap32;
+ auto it = annexMap.find(annex);
+ if (it == annexMap.end())
+ return false;
+ output = it->second;
+ return true;
+}
+
BaseGdbRegCache*
RemoteGDB::gdbRegs()
{
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index 10fcb6d..c53357b 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -1,7 +1,7 @@
/*
* Copyright 2015 LabWare
* Copyright 2014 Google, Inc.
- * Copyright (c) 2013, 2016 ARM Limited
+ * Copyright (c) 2013, 2016, 2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -50,6 +50,7 @@
#include <algorithm>
+#include "arch/arm/registers.hh"
#include "arch/arm/utility.hh"
#include "base/compiler.hh"
#include "base/remote_gdb.hh"
@@ -71,9 +72,9 @@
private:
struct {
uint32_t gpr[16];
- uint32_t fpr[8*3];
- uint32_t fpscr;
uint32_t cpsr;
+ uint64_t fpr[32];
+ uint32_t fpscr;
} M5_ATTR_PACKED r;
public:
char *data() const { return (char *)&r; }
@@ -97,6 +98,8 @@
uint64_t pc;
uint32_t cpsr;
VecElem v[NumVecV8ArchRegs * NumVecElemPerVecReg];
+ uint32_t fpsr;
+ uint32_t fpcr;
} M5_ATTR_PACKED r;
public:
char *data() const { return (char *)&r; }
@@ -112,10 +115,27 @@
AArch32GdbRegCache regCache32;
AArch64GdbRegCache regCache64;
+ static const uint8_t gdb_xml_arm_target[];
+ static const size_t gdb_xml_arm_target_len;
+ static const uint8_t gdb_xml_arm_core[];
+ static const size_t gdb_xml_arm_core_len;
+ static const uint8_t gdb_xml_arm_vfpv3[];
+ static const size_t gdb_xml_arm_vfpv3_len;
+ static const uint8_t gdb_xml_aarch64_target[];
+ static const size_t gdb_xml_aarch64_target_len;
+ static const uint8_t gdb_xml_aarch64_core[];
+ static const size_t gdb_xml_aarch64_core_len;
+ static const uint8_t gdb_xml_aarch64_fpu[];
+ static const size_t gdb_xml_aarch64_fpu_len;
public:
RemoteGDB(System *_system, ThreadContext *tc, int _port);
BaseGdbRegCache *gdbRegs();
+ std::vector<std::string> availableFeatures() const
+ {
+ return {"qXfer:features:read+"};
+ };
+ bool getAnnex(const std::string& annex, std::string& output);
};
} // namespace ArmISA
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id15b7aeccca824c342e49a626d2877179474f3d4
Gerrit-Change-Number: 15138
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli <[email protected]>
Gerrit-MessageType: newchange
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