Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/15599
Change subject: arch-arm: Inital vector rename mode depending on A32/A64
......................................................................
arch-arm: Inital vector rename mode depending on A32/A64
Change-Id: I6b99833641b0ab6534471d5ff3ca5d3791285481
---
M src/arch/arm/ArmISA.py
M src/arch/arm/isa.cc
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 52c42cb..b4e8536 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -87,10 +87,6 @@
id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
"AArch64 Auxiliary Feature Register 1")
- # Initial vector register rename mode
- vecRegRenameMode = Param.VecRegRenameMode('Full',
- "Initial rename mode for vecregs")
-
# 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
"AArch64 Debug Feature Register 0")
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d7d51b8..1a1deb9 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -62,7 +62,6 @@
: SimObject(p),
system(NULL),
_decoderFlavour(p->decoderFlavour),
- _vecRegRenameMode(p->vecRegRenameMode),
pmu(p->pmu),
impdefAsNop(p->impdef_nop)
{
@@ -103,6 +102,9 @@
haveGICv3CPUInterface = true;
}
+ // Initial rename mode depends on highestEL
+ _vecRegRenameMode = highestELIs64 ? Enums::Full : Enums::Elem;
+
initializeMiscRegMetadata();
preUnflattenMiscReg();
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I6b99833641b0ab6534471d5ff3ca5d3791285481
Gerrit-Change-Number: 15599
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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