Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/15600
Change subject: cpu: O3 rename using the flatIndex instead of index
......................................................................
cpu: O3 rename using the flatIndex instead of index
This patch is replacing the RegId::index with RegId::flatIndex so that
it provides a valid register number when used by a VecElem register.
Change-Id: I5b000abb9457cd325c2a3021e772a75ea33d8a4c
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/cpu/o3/rename_map.cc
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index d1876a9..1b831d9 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -76,14 +76,14 @@
PhysRegIdPtr renamed_reg;
// Record the current physical register that is renamed to the
// requested architected register.
- PhysRegIdPtr prev_reg = map[arch_reg.index()];
+ PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()];
// If it's not referencing the zero register, then rename the
// register.
if (arch_reg != zeroReg) {
renamed_reg = freeList->getReg();
- map[arch_reg.index()] = renamed_reg;
+ map[arch_reg.flatIndex()] = renamed_reg;
} else {
// Otherwise return the zero register so nothing bad happens.
assert(prev_reg->isZeroReg());
@@ -92,8 +92,8 @@
DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping
was"
" %d (%d)\n",
- arch_reg, renamed_reg->index(), renamed_reg->flatIndex(),
- prev_reg->index(), prev_reg->flatIndex());
+ arch_reg, renamed_reg->flatIndex(), renamed_reg->flatIndex(),
+ prev_reg->flatIndex(), prev_reg->flatIndex());
return RenameInfo(renamed_reg, prev_reg);
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5b000abb9457cd325c2a3021e772a75ea33d8a4c
Gerrit-Change-Number: 15600
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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