Hello Giacomo Gabrielli,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/15615
to review the following change.
Change subject: cpu, arm: Fix usage of VecElem
......................................................................
cpu, arm: Fix usage of VecElem
* RegId() constructor requires three arguments in case of a VecElem
register: the class, the vector index and the element index inside the
vector, otherwise it panics.
* setArchVecElem should create a VecElemClass RegId, and not a VecRegClass.
Initializing a VecRegClass with three arguments makes it panic
Change-Id: Ic842df4dcddaffa83b211aa6e1dd1953cafa4951
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
---
M src/arch/arm/isa.hh
M src/cpu/o3/cpu.cc
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 1ec0f46..2b1bdcb 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -444,7 +444,8 @@
case VecRegClass:
return RegId(VecRegClass, flattenVecIndex(regId.index()));
case VecElemClass:
- return RegId(VecElemClass,
flattenVecElemIndex(regId.index()));
+ return RegId(VecElemClass,
flattenVecElemIndex(regId.index()),
+ regId.elemIndex());
case CCRegClass:
return RegId(CCRegClass, flattenCCIndex(regId.index()));
case MiscRegClass:
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index e5b8103..8f399e9 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1466,7 +1466,7 @@
const VecElem& val, ThreadID tid)
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
- RegId(VecRegClass, reg_idx, ldx));
+ RegId(VecElemClass, reg_idx, ldx));
setVecElem(phys_reg, val);
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ic842df4dcddaffa83b211aa6e1dd1953cafa4951
Gerrit-Change-Number: 15615
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
Gerrit-MessageType: newchange
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