Hello Giacomo Gabrielli,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/15655
to review the following change.
Change subject: cpu: Fix usage of setArchVecElem
......................................................................
cpu: Fix usage of setArchVecElem
setArchVecElem should create a VecElemClass RegId, and not a VecRegClass.
Initializing a VecRegClass with three arguments makes it panic
Change-Id: I6c398d67305bfe7bea12cb02edd4f4c3a202e69a
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/cpu/o3/cpu.cc
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index e5b8103..8f399e9 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1466,7 +1466,7 @@
const VecElem& val, ThreadID tid)
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
- RegId(VecRegClass, reg_idx, ldx));
+ RegId(VecElemClass, reg_idx, ldx));
setVecElem(phys_reg, val);
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I6c398d67305bfe7bea12cb02edd4f4c3a202e69a
Gerrit-Change-Number: 15655
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Giacomo Gabrielli <giacomo.gabrie...@arm.com>
Gerrit-MessageType: newchange
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