Hello Jason Lowe-Power,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/15836
to review the following change.
Change subject: tests: Convert memtest to new framework
......................................................................
tests: Convert memtest to new framework
Change-Id: I58be6fb1675f6502d6644d502915df80aa197a4a
Signed-off-by: Jason Lowe-Power <[email protected]>
---
A tests/gem5/memory/memtest-run.py
A tests/gem5/memory/ref/memtest.stderr
M tests/gem5/memory/simple-run.py
M tests/gem5/memory/test.py
4 files changed, 177 insertions(+), 12 deletions(-)
diff --git a/tests/gem5/memory/memtest-run.py
b/tests/gem5/memory/memtest-run.py
new file mode 100644
index 0000000..c454160
--- /dev/null
+++ b/tests/gem5/memory/memtest-run.py
@@ -0,0 +1,85 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../../../configs/')
+from common.Caches import *
+
+#MAX CORES IS 8 with the fals sharing method
+nb_cores = 8
+cpus = [MemTest(max_loads = 1e5, progress_interval = 1e4)
+ for i in xrange(nb_cores) ]
+
+# system simulated
+system = System(cpu = cpus,
+ physmem = SimpleMemory(),
+ membus = SystemXBar())
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain =
system.voltage_domain)
+
+system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
+system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB',
assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+
+# connect l2c to membus
+system.l2c.mem_side = system.membus.slave
+
+# add L1 caches
+for cpu in cpus:
+ # All cpus are associated with cpu_clk_domain
+ cpu.clk_domain = system.cpu_clk_domain
+ cpu.l1c = L1Cache(size = '32kB', assoc = 4)
+ cpu.l1c.cpu_side = cpu.port
+ cpu.l1c.mem_side = system.toL2Bus.slave
+
+system.system_port = system.membus.slave
+
+# connect memory to membus
+system.physmem.port = system.membus.master
+
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( full_system = False, system = system )
+root.system.mem_mode = 'timing'
+
+m5.instantiate()
+exit_event = m5.simulate()
+if exit_event.getCause() != "maximum number of loads reached":
+ exit(1)
+
diff --git a/tests/gem5/memory/ref/memtest.stderr
b/tests/gem5/memory/ref/memtest.stderr
new file mode 100644
index 0000000..8aeb9b8
--- /dev/null
+++ b/tests/gem5/memory/ref/memtest.stderr
@@ -0,0 +1,74 @@
+info: Entering event queue @ 0. Starting simulation...
+system.cpu2: completed 10000 read, 5473 write accesses @58566500
+system.cpu6: completed 10000 read, 5523 write accesses @59843500
+system.cpu5: completed 10000 read, 5528 write accesses @59904000
+system.cpu7: completed 10000 read, 5514 write accesses @60034500
+system.cpu0: completed 10000 read, 5658 write accesses @60233500
+system.cpu3: completed 10000 read, 5550 write accesses @60702500
+system.cpu4: completed 10000 read, 5695 write accesses @60917500
+system.cpu1: completed 10000 read, 5725 write accesses @61099500
+system.cpu2: completed 20000 read, 10969 write accesses @109573500
+system.cpu5: completed 20000 read, 10959 write accesses @111117500
+system.cpu3: completed 20000 read, 11038 write accesses @111396500
+system.cpu0: completed 20000 read, 11218 write accesses @111506000
+system.cpu4: completed 20000 read, 11202 write accesses @111558000
+system.cpu7: completed 20000 read, 11032 write accesses @111670500
+system.cpu6: completed 20000 read, 11032 write accesses @111779000
+system.cpu1: completed 20000 read, 11327 write accesses @113231500
+system.cpu2: completed 30000 read, 16515 write accesses @161507000
+system.cpu0: completed 30000 read, 16644 write accesses @162395000
+system.cpu7: completed 30000 read, 16545 write accesses @162882500
+system.cpu3: completed 30000 read, 16513 write accesses @163027000
+system.cpu6: completed 30000 read, 16475 write accesses @163034500
+system.cpu5: completed 30000 read, 16469 write accesses @163300000
+system.cpu4: completed 30000 read, 16897 write accesses @163344000
+system.cpu1: completed 30000 read, 16913 write accesses @164885000
+system.cpu0: completed 40000 read, 22123 write accesses @213066500
+system.cpu2: completed 40000 read, 22089 write accesses @213473000
+system.cpu6: completed 40000 read, 21968 write accesses @214022000
+system.cpu5: completed 40000 read, 21906 write accesses @214049000
+system.cpu3: completed 40000 read, 22031 write accesses @214263000
+system.cpu7: completed 40000 read, 22229 write accesses @214976000
+system.cpu4: completed 40000 read, 22554 write accesses @215424500
+system.cpu1: completed 40000 read, 22442 write accesses @217521500
+system.cpu0: completed 50000 read, 27709 write accesses @263850000
+system.cpu2: completed 50000 read, 27612 write accesses @264790500
+system.cpu3: completed 50000 read, 27566 write accesses @265777000
+system.cpu6: completed 50000 read, 27538 write accesses @265782000
+system.cpu7: completed 50000 read, 27685 write accesses @266141500
+system.cpu5: completed 50000 read, 27548 write accesses @266553000
+system.cpu4: completed 50000 read, 28257 write accesses @267147000
+system.cpu1: completed 50000 read, 27983 write accesses @269091000
+system.cpu0: completed 60000 read, 33078 write accesses @314408000
+system.cpu2: completed 60000 read, 33072 write accesses @315865000
+system.cpu5: completed 60000 read, 32995 write accesses @317291000
+system.cpu3: completed 60000 read, 33143 write accesses @317543000
+system.cpu4: completed 60000 read, 33625 write accesses @317708500
+system.cpu6: completed 60000 read, 33157 write accesses @318055000
+system.cpu7: completed 60000 read, 33258 write accesses @318228500
+system.cpu1: completed 60000 read, 33452 write accesses @319797500
+system.cpu0: completed 70000 read, 38678 write accesses @365094500
+system.cpu2: completed 70000 read, 38556 write accesses @367862000
+system.cpu5: completed 70000 read, 38571 write accesses @368721000
+system.cpu7: completed 70000 read, 38701 write accesses @369173000
+system.cpu6: completed 70000 read, 38748 write accesses @369193000
+system.cpu3: completed 70000 read, 38709 write accesses @369417500
+system.cpu4: completed 70000 read, 39130 write accesses @369476500
+system.cpu1: completed 70000 read, 38979 write accesses @370747000
+system.cpu0: completed 80000 read, 44199 write accesses @416948000
+system.cpu2: completed 80000 read, 44125 write accesses @418910500
+system.cpu5: completed 80000 read, 44009 write accesses @419509500
+system.cpu4: completed 80000 read, 44684 write accesses @420399000
+system.cpu6: completed 80000 read, 44359 write accesses @421077500
+system.cpu7: completed 80000 read, 44242 write accesses @421366000
+system.cpu3: completed 80000 read, 44262 write accesses @421560000
+system.cpu1: completed 80000 read, 44523 write accesses @422115500
+system.cpu0: completed 90000 read, 49818 write accesses @468627500
+system.cpu2: completed 90000 read, 49680 write accesses @469870500
+system.cpu5: completed 90000 read, 49407 write accesses @470722000
+system.cpu4: completed 90000 read, 50231 write accesses @472043000
+system.cpu7: completed 90000 read, 49777 write accesses @472284500
+system.cpu3: completed 90000 read, 49703 write accesses @472306500
+system.cpu6: completed 90000 read, 49992 write accesses @472978000
+system.cpu1: completed 90000 read, 50145 write accesses @474732500
+system.cpu0: completed 100000 read, 55341 write accesses @520307000
diff --git a/tests/gem5/memory/simple-run.py
b/tests/gem5/memory/simple-run.py
index b77c23c..28ddce6 100644
--- a/tests/gem5/memory/simple-run.py
+++ b/tests/gem5/memory/simple-run.py
@@ -47,17 +47,14 @@
args = parser.parse_args()
-# both traffic generator and communication monitor are only available
-# if we have protobuf support, so potentially skip this test
-# require_sim_object("TrafficGen")
-# require_sim_object("CommMonitor")
-# This needs to be fixed in the new infrastructure
-
# even if this is only a traffic generator, call it cpu to make sure
# the scripts are happy
-cpu = TrafficGen(
- config_file=os.path.join(os.path.dirname(os.path.abspath(__file__)),
+try:
+ cpu = TrafficGen(
+
config_file=os.path.join(os.path.dirname(os.path.abspath(__file__)),
"tgen-simple-mem.cfg"))
+except NameError:
+ m5.fatal("protobuf required for simple memory test")
class MyMem(SimpleMemory):
if args.bandwidth:
@@ -99,5 +96,5 @@
m5.instantiate()
exit_event = m5.simulate(100000000000)
-
-print(exit_event.getCause())
+if exit_event.getCause() != "simulate() limit reached":
+ exit(1)
diff --git a/tests/gem5/memory/test.py b/tests/gem5/memory/test.py
index 597d4f0..466a08d 100644
--- a/tests/gem5/memory/test.py
+++ b/tests/gem5/memory/test.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2018 The Regents of the University of California.
+# Copyright (c) 2016 The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -31,6 +31,8 @@
'''
from testlib import *
+ref_path = joinpath(getcwd(), 'ref')
+
gem5_verify_config(
name='simple_mem_default',
verifiers=(), # No need for verfiers this will return non-zero on fail
@@ -58,5 +60,12 @@
config=joinpath(getcwd(), 'simple-run.py'),
config_args = args,
valid_isas=(constants.null_tag,),
- )
+ ) # This tests for validity as well as performance
+gem5_verify_config(
+ name='memtest',
+
verifiers=(verifier.MatchStderr(joinpath(ref_path, 'memtest.stderr')),),
+ config=joinpath(getcwd(), 'memtest-run.py'),
+ config_args = [],
+ valid_isas=(constants.null_tag,),
+)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15836
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I58be6fb1675f6502d6644d502915df80aa197a4a
Gerrit-Change-Number: 15836
Gerrit-PatchSet: 1
Gerrit-Owner: Ayaz Akram <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: newchange
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